A 0.35μm 600V ultra-thin epitaxial BCD technology for high voltage gate driver IC is developed in this work, including 600V LDMOS, 600V isolation ring, asymmetric 20V NMOS, asymmetric 20V PMOS, symmetric 20V NMOS, symmetric 20V PMOS and BJT. Only 15 photo layers are used for the proposed 1P2M technology. The experimental devices demonstrate that the BVs of divided RESURF structures are 770V, and the isolation BVs between V D of the 600V LDMOS and high side V B are above 30V. The off-state BVs of the NMOS and the PMOS structures are greater than 38V, respectively, while the current capacity in the same area is doubled, namely, the area of the CMOS driver is decreased by 50% at least at same drive capability, compared with the competitor A.

A 0.35μm 600V ultra-thin epitaxial BCD technology for high voltage gate driver IC

In this work, the effect of different drift region lengths on the ESD ability in ultra-high voltage LDMOS is proposed and verified via a 0.5 μm 300 V process. By the different drift-region lengths, the corresponding breakdown voltage can result in the corresponding trigger voltage, holding voltage and secondary breakdown current. As the drift-region length decreases, V t1 and V h values will decrease both too. Eventually, as the drift-region length is 5.8 μm, the optimized secondary breakdown current can be upgraded to 6.842 A. The overall DUTs has higher ESD ability than that of the reference group.

Evaluating the Drift-Region Length Effect of nLDMOS on ESD Ability with a TLP Testing System

The weak ESD-immunity problem has been deeply persecuted in ultra high-voltage (UHV) metal-oxide-semiconductor field-effect transistors (MOSFETs) and urgently needs to be solved. In this paper, a UHV 300 V circular n-channel (n) lateral diffused MOSFET (nLDMOS) is taken as the benchmarked reference device for the electrostatic discharge (ESD) capability improvement. However, a super-junction (SJ) structure in the drain region will cause extra depletion zones in the long drain region and reduce the peak value of the channel electric field. Therefore, it may directly increase the resistance of the device to ESD. Then, in this reformation project for UHV nLDMOSs to ESD, two strengthening methods were used. Firstly, the SJ area ratio changed by the symmetric eight-zone elliptical-cylinder length (X) variance (i.e., X = 5, 10, 15 and 20 μm) is added into the drift region of drain side to explore the influence on ESD reliability. From the experimental results, it could be found that the breakdown voltages (VBK) were changed slightly after adding this SJ structure. The VBK values are filled between 391 and 393.5 V. Initially, the original reference sample is 393 V; the VBK changing does not exceed 0.51%, which means that these components can be regarded as little changing in the conduction characteristic after adding these SJ structures under the normal operating conditions. In addition, in the ESD transient high-voltage bombardment situation, the human-body model (HBM) capability of the original reference device is 2500 V. Additionally, as SJs with the length X high-voltage P-type well (HVPW) are inserted into the drain-side drift region, the HBM robustness of these UHV nLDMOSs increases with the length X of the HVPW. When the length X (HVPW) is 20 μm, the HBM value can be upgraded to a maximum value of 5500 V, the ESD capability is increased by 120%. A linear relationship between the HBM immunity level and area ratio of SJs in the drains side in this work can be extracted. The second part revealed that, in the symmetric four-zone elliptical cylinder SJ modulation, the HBM robustness is generally promoted with the increase of HVPW SJ numbers (the highest HBM value (4500 V) of the M5 device improved by 80% as compared with the reference device under test (DUT)). Therefore, from this work, we can conclude that the addition of symmetric elliptical-cylinder SJ structures into the drain-side drift region of a UHV nLDMOS is a good strategy for improving the ESD immunity.

https://www.mdpi.com/2079-9292/9/5/730/pdf

Robust ESD-Reliability Design of 300-V Power N-Channel LDMOSs with the Elliptical Cylinder Super-Junctions in the Drain Side

Electrostatic discharge (ESD) events are the main factors impacting the reliability of Integrated circuits (ICs); therefore, the ESD immunity level of these ICs is an important index. This paper focuses on comprehensive drift-region engineering for ultra-high-voltage (UHV) circular n-channel lateral diffusion metal-oxide-semiconductor transistor (nLDMOS) devices used to investigate impacts on ESD ability. Under the condition of fixed layout area, there are four kinds of modulation in the drift region. First, by floating a polysilicon stripe above the drift region, the breakdown voltage and secondary breakdown current of this modulation can be increased. Second, adjusting the width of the field-oxide layer in the drift region when the width of the field-oxide layer is 5.8 μm will result in the minimum breakdown voltage (105 V) but the best secondary breakdown current (6.84 A). Third, by adjusting the discrete unit cell and its spacing, the corresponding improved trigger voltage, holding voltage, and secondary breakdown current can be obtained. According to the experimental results, the holding voltage of all devices under test (DUTs) is greater than that of the reference group, so the discrete HV N-Well (HVNW) layer can effectively improve its latch-up immunity. Finally, by embedding different P-Well lengths, the findings suggest that when the embedded P-Well length is 9 μm, it will have the highest ESD ability and latch-up immunity.

https://www.mdpi.com/2079-9292/8/12/1469/pdf

Electrostatic-Discharge-Immunity Impacts in 300 V nLDMOS by Comprehensive Drift-Region Engineering

Single-event burnout hardening evaluation with current and electric field redistribution of high voltage LDMOS transistors based on TCAD Simulations

A new concept to realize self-protected ESD structure for 700V high side gate drive IC without additional process steps and area penalty is presented. The device was verified by simulation and confirmed by experimental results. A parasitic NPN structure integrated in high voltage level shifter LDMOS enables LDMOS to be operated within safe operating area when ESD strikes the high side driver part with respect to the low voltage controller by triggering snapback right after breakdown. The new ESD self-protected LDMOS and high voltage junction termination structure in conjunction with parasitic NPN showed remarkable improvement in HBM ESD level from 1.4kV to 6.8kV.

Hiromi Endoh

Papers

A new ESD self-protection structure for 700V high side gate drive IC