A semiconductor device packaged adapter for electrically coupling contacts on a first circuit member to contacts on a second circuit member. The adapter typically includes first and second substrates, each with arrays of terminals. Proximal ends of the first terminals on the first substrate are arranged to be soldered to the contacts on the first circuit member and proximal ends of the second terminals on the second substrate are arranged to be soldered to the contacts on the second circuit member. Complementary engaging structures located on distal ends of the first and second terminals engage to electrically and mechanically couple the first circuit member to the second circuit member.

Semiconductor device package adapter

A surface mount electrical interconnect adapted to provide an interface between solder balls on a BGA device and a PCB. The electrical interconnect includes a socket substrate with a first surface, a second surface, and a plurality of openings sized and configured to receive the solder balls on the BGA device. A plurality of electrically conductive contact tabs are bonded to the first surface of the socket substrate so that contact tips on the contact tabs extend into the openings. The contact tips electrically couple with the BGA device when the solder balls are positioned in the openings. Vias are located in the openings that electrically couple the contact tabs to contact pads located proximate the second surface of the socket substrate. Solder balls are bonded to the contact pad that are adapted to electrically and mechanically couple the electrical interconnect to the PCB.

High performance surface mount electrical interconnect

An integrated circuit (IC) package for an IC device, and a method of making the same The IC package includes an interconnect assembly with at least one printed compliant layer, a plurality of first contact members located along a first major surface, a plurality of second contact members located along a second major surface, and a plurality of printed conductive traces electrically coupling a plurality of the first and second contact members The compliant layer is positioned to bias at least the first contact members against terminals on the IC device Packaging substantially surrounds the IC device and the interconnect assembly The second contact members are accessible from outside the packaging

Compliant printed circuit area array semiconductor device package

An interconnect assembly including a resilient material with a plurality of through holes extending from a first surface to a second surface. A plurality of discrete, free-flowing conductive particles is located in the through holes. The conductive particles are preferably substantially free of non-conductive materials. A plurality of first contact tips are located in the through holes adjacent the first surface and a plurality of second contact tips are located in the through holes adjacent the second surface. The resilient material provides the required resilience, while the conductive particles provide a conductive path substantially free of non-conductive materials.

Resilient conductive electrical interconnect

A surface mount electrical interconnect adapted to provide an interface between contact pads on an LGA device and a PCB. The electrical interconnect includes a socket substrate having a first surface with a plurality of first openings having first cross-sections, a second surface with a plurality of second openings having second cross-sections, and center openings connecting the first and second openings. The center openings include at least one cross-section greater than the first and second cross-sections. A plurality of contact members are located in the socket substrate such that first contact tips are located proximate the first openings, second contact tips are located proximate the second openings, and center portions located in the center openings.

Electrical interconnect ic device socket

A multilayered circuit board of the present invention has a single-side laminated structure and does not include a core substrate having via-holes formed therethrough and vias for providing electrical connection through the via-holes. The multilayered circuit board includes a plurality of pairs of layers, each pair including a conductor circuit layer and an insulator layer, wherein a glass transition temperature of each insulator layer is 170° C. or higher, a coefficient of thermal expansion at the glass transition temperature or lower of each insulator layer is 35 ppm or less, and a modulus of elasticity of each insulator layer is 5 GPa or more.

Multilayered circuit board and semiconductor device

This invention provides a multiple layer circuit board having a plurality of sets of conductive circuit layers and insulation layers laminated on one side without having a core board which contains through holes forming conductive connections by via connections, wherein each insulation layer is characterized by having a glass transition temperature of 170 DEG C or higher, a linear expansion coefficient below the glass transition temperature of 35 ppm, and a modulus of elasticity of 5 GPa or higher

Hironori Maruyama

Papers

Multilayered circuit board and semiconductor device

Multiple circuit board and semiconductor device