scispace - formally typeset
H

Hiroshi Hosokawa

Researcher at Canon Inc.

Publications -  6
Citations -  144

Hiroshi Hosokawa is an academic researcher from Canon Inc.. The author has contributed to research in topics: Image processing & Signal. The author has an hindex of 4, co-authored 6 publications receiving 144 citations.

Papers
More filters
Patent

Method and apparatus for image processing with fed-back error correction

TL;DR: In this paper, an image processing apparatus consisting of a binarization circuit to binarize image data by a predetermined threshold value, a processor to correct errors generated in binarisation, a first detector to detect an edge direction of the image from the image data, and a second detector to detecting an edge quantum of the input image from image data.
Patent

Image processing apparatus with binarization-error dispersal

TL;DR: In this article, an image processing apparatus for digitizing an analog image by dispersing the digitizing error to the surrounding areas is presented. The characteristics or edge of the analog image are identified, and the error dispersing area is varied according to the result of identification, enabling reproduction of the image with high quality regardless of the nature of the original image.
Patent

Image processing method

TL;DR: In this article, the edge component of an image and the size of a diffusion matrix in an error diffusing method were used to reproduce the image of any original with high quality and high accuracy.
Patent

Logic verification device and method of memory control circuit

TL;DR: In this article, a verification test program and a CPU model request an access to a memory model 105 for the memory control circuit and a transaction monitor 104 monitors the transaction generated on a system bus 103 by the access requested by the CPU model 101 and holds transaction information based on the monitoring.
Patent

Logical verification apparatus and method for memory control circuit

TL;DR: In this paper, a memory access checker logically verifies the memory control circuit using the transaction information acquired by the memory model, and transaction information held by the transaction monitor, and detects and holds a transaction of memory access from the CPU model.