A semiconductor integrated circuit has a central processing unit and a rewritable nonvolatile memory area disposed in an address space of the central processing unit. The nonvolatile memory area has a first nonvolatile memory area and a second nonvolatile memory area, which memorize information depending on the difference of threshold voltages. The first nonvolatile memory area has the maximum variation width of a threshold voltage for memorizing information set larger than that of the second nonvolatile memory area. When the maximum variation width of the threshold voltage for memorizing information is larger, since stress to a memory cell owing to a rewrite operation of memory information becomes larger, it is inferior in a point of guaranteeing the number of times of rewrite operation; however, since a read current becomes larger, a read speed of memory information can be expedited. The first nonvolatile memory area can be prioritized to expedite a read speed of the memory information and the second nonvolatile memory area can be prioritized in guaranteeing the number of times of rewrite operation of memory information more.

Semiconductor Integrated circuit

PURPOSE:To enable a fine MOS transistor with high performance to be used, by providing two level conversion circuits provided with inverter circuits which shift an inputted small amplitude signal to a high level side and a low level side and a large amplitude generation circuit, and setting the output of the large amplitude generation circuit as that of the level conversion circuit. CONSTITUTION:When an input signal Vin is set at a low level(0V), the output VH of a first level conversion circuit 4 is shifted to an external high potential power source Vcc level, and the output VL of a second level conversion circuit 5 to an internal constant power source VDD level. Thereby, no external constant power source VEE is applied on a pMOS transistor by setting the output VOUT of the large amplitude generation circuit 6 at the external constant voltage source VEE. Also, when the input signal Vin is set at a high level, no high voltage is applied between the gates and the drains, and the gates and the sources of MOS transistors T9-T12 by shifting the VH to the VDD level, and the VL to the VEE level, and setting the VOUT at the VCC level, the fine MOS transistor with small pressure resistance can be used.

Level conversion circuit

PURPOSE:To attain circuit integration and high speed operation by operating a switching element impresses a high voltage in response to the operation of an additional switching element operated at a low voltage level of the logic circuit operation being the result of differentiation of an on/off input signal via an RC differentiation circuit. CONSTITUTION:A resistor 42 and a capacitor 41 of a level conversion circuit 4 differentiate an input signal S2. When a gate voltage of a transistor (TR) 43 exceeds its threshold value, the TR 43 is turned on. A high voltage VH to be level-converted is divided by resistors 44, 45 and a bias voltage is fed to a TR 46. A bias voltage is changed by the on/off operation of the TR 43 and when the gate voltage of the TR 46 is lowered than its threshold voltage, the TR 46 is turned on. When the TR 26 of push-pull connection is turned on and a TR 3 is turned off, an output Sout reaches a high voltage VH and other levels are zero V. Since no high voltage VH is impressed to a capacitor 41, no high dielectric strength is required and then circuit integration is facilitated. Since the TR 46 is operated by the TR 43, high speed operation is attained.

Level converting circuit

PURPOSE:To remove the dispersion of a level shift quantity especially on the low level side and to obtain an optionally level-shifted low level output by connecting resistor elements between an output part of a logical gate and a power supply and extracting a level shifted output from a node between the resistor elements CONSTITUTION:Serial resistors R1, R2 are connected in parallel with an FET Q1 having constant current characteristics as a load element and an output voltage VOUT is extracted from a node between the resistors R1, R2 Thereby, the low level output can be optionally controlled by controlling the resistance values of the resistors R1, R2 When a depression type FET shorted between the drain and gate is used as the resistor element, the resistor element stabilized against the dispersion of the threshold voltage or the like of the FET can be obtained and the resistor element excellent in uniformity and controllability can be obtained

Logical level control circuit

PURPOSE:To decrease the number of elements, by connecting the first polarity transistor which has connected an output of the low voltage side and the reverse potential to the source and the gate, respectively, to the second polarity transistor, in a level converting circuit consisting of an IGFET. CONSTITUTION:In a level converting circuit consisting of an IGFET, reverse output potential V1 of the low voltage side by an inverter 21 is inputted directly to a P channel transistor TR24, also is inputted to a gate Vi of an N channel TR25 which has been by-passed to source potential VSS by a resister 23 through a capacity 22, and each drain of the trasistors 24, 25 is connected to each other and outputs voltage V0. Moreover, the reverse voltage V1 and the voltage V0 are connected to the source of a P channel TR26 and the gate, respectively, and its drain is connected to the gate of the transistor 25. Accordingly, since the TRs 24, 25 execute a push- pull operation to each other, the power consumption is reduced, and furthermore, when the reverse voltage V1 has become high voltage VDD as a direct current, the voltage V0 is set to the source potential VSS stably.

PURPOSE:To obtain the output voltage of high potential with the input signal of low voltage, by constituting C-MOS inverter circuit with MOSFET of P and N channel, further providing N channel MOSFET and applying the input signal of opposite phase to the gate. CONSTITUTION:C-MOS circuit is constituted with the P channel MOSFET T21 200V or more in dielectric strength and the N channel MOSFET T22 having the same breakdown voltage. Further, branching resistors R21 and R22 are provided, the junction point is connected to the gate of the element T21, and one end is connected to the gate of the element T22 via the inverter INV consisting of C-MOS via the N channel MOSFET T23. With this constitution, the power supply VDD is applied to the element T21 and the resistor R21, and when the input VIN is fed to the element T23 and the inverter INV, high voltage output signal having opposite phase as the input signal is appeared at the output Vout.

Hiroshi Sato

Papers

C-mos circuit of high voltage operation