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Hiroshi Wabuka

Researcher at NEC

Publications -  14
Citations -  97

Hiroshi Wabuka is an academic researcher from NEC. The author has contributed to research in topics: Integrated circuit & Transistor. The author has an hindex of 6, co-authored 14 publications receiving 97 citations.

Papers
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Patent

Electromagnetic interference suppressing device and circuit

TL;DR: In this paper, the electromagnetic interference suppressing device of the present invention includes a plurality of connection layers and ground layers formed of a conductive material, alternately layered with an insulating layer.
Patent

Method for designing a power supply decoupling circuit

TL;DR: In this paper, a design support system 100 according to the present invention comprises: an LSI library 10, in which rated characteristics of various LSIs are stored by an LSIs library preparation unit 70; a decoupling capacitor library 20, in the presence of various capacitors are stored; a PCB library 30, where the cross-sectional structures of various power wiring lines are stored.
Patent

Power model for EMI simulation to semiconductor integrated circuit , method of designing the power model, EMI simulator, power model preparation computer program, and storage medium storing the same as well as power model design support system

TL;DR: In this paper, a power model for a semiconductor integrated circuit is presented, where the power model comprises a logic gate circuit part representing an operating part of the integrated circuit and an equivalent internal capacitive part representing a non-operating part.
Patent

Method for designing a decoupling circuit

TL;DR: In this article, a method for designing a decoupling circuit for a source line of a LSI includes the steps of determining the capacitance of the decoupled capacitor based on the electric charge necessary for one cycle operation of the LSI and the allowable fluctuation of the source voltage.
Patent

Method and apparatus for preparing a simulation model for semiconductor integrated circuit at power terminal for simulating electromagnetic interference

TL;DR: In this article, a model for a circuit for simulating an electromagnetic interference was proposed, where the model was described by a combination of at least one variable resistance and load capacitance.