A digital computer system includes a scalar CPU, a vector processor, and a shared cache memory. The scalar CPU has an execution unit, a memory management unit, and a cache controller unit. The execution unit generates load/store memory addresses for vector load/store instructions. The load/store addresses are translated by the memory management unit, and stored in a write buffer that is also used for buffering scalar write addresses and write data. The cache controller coordinates-loads and stores between the vector processor and the shared cache with scalar reads and writes to the cache. Preferably the cache controller permits scalar reads to precede scalar writes and vector load/stores by checking for conflicts with scalar writes and vector load/stores in the write queue, and also permits vector load/stores to precede vector operates by checking for conflicts with vector operate information stored in a vector register scoreboard. Preferably the cache controller includes vector logic which is responsive to vector information written in intra-processor registers by the execution unit. The vector logic keeps track of the vector length and blocks extra memory addresses generated by the execution unit for the vector elements. The vector logic also blocks the memory addresses of masked vector elements so that these addresses are not translated by the memory management unit.

Digital computer system with cache controller coordinating both vector and scalar operations

A system and method are disclosed, according to which, the responsiveness of client/server-based distributed web applications operating in an object-oriented environment may be improved by storing both JSPs and commands in the same cache. Some of the code and data structures required for caching JSPs are the same as for commands, and are saved in a common area of the cache. A second area of the cache is reserved for code and data specific to JSPs, and a third area is reserved for code and data specific to commands. This arrangement avoids the difficulty of judiciously apportioning the available cache between JSPs and commands.

Integrated JSP and command cache for web applications with dynamic content

A personal computer has a memory system including a write-through cache which is accessible by more than one device. A snoop mechanism includes logic that monitors bus master control signals to determine if a new memory write cycle has been started before a current snoop cycle has finished. If a new cycle has been started, then a corresponding snoop cycle occurs which overlaps the new memory cycle and is pipelined with the previous snoop cycle so that the snooping mechanism does not fall behind the memory write cycles.

Personal computer having memory system with write-through cache and pipelined snoop cycles

A cache memory system for use during vector processing in a processor The processor contains a central processing unit (CPU) and a main memory The system includes a vector cache memory, a first address register, a main memory address calculation unit, and a cache address calculation unit The first register stores a first address associated with an instruction executed by the CPU The main memory address calculation unit is coupled to the first address register for calculating a second address utilizing the first address and vector stride data associated with said executed instruction The second address is utilized to access the main memory The cache address calculation unit is coupled to both the first address register and the main memory address calculation unit for calculating the third address utilizing portions of the first address and portions of the second address The third address is utilized to access the vector cache memory

Cache memory system for vector processing

A system and method are disclosed, according to which, the responsiveness of client/server-based distributed web applications operating in an object-oriented environment may be improved by detecting and handling affinity breaks between a client and server. Affinity exists when a client's requests are all routed to the same server. This is often the case, for example, during secure online transactions. A problem occurs when the preferred server becomes temporarily unavailable, and the client's requests are directed to a different server. When the original server is restored, it must detect the fact that its affinity with the client was disrupted, and any client-specific data in its cache may be invalid. In an exemplary embodiment of the system and method disclosed herein, an “affinity command” is exchanged between the client and the server during each client request. The affinity command contains a user ID associated with the client and a “generation ID”, which is unique for each request. When a request is received from a client, the server examines the generation ID in the accompanying affinity command and compares it to its internally recorded value. If they match, the server knows it has not missed any requests. In this case, the server updates the generation ID and sends the new value back to the client, along with the requested cache entry. If the generation ID received from the client fails to match the recorded value, an affinity break is detected, and the server updates its cache from the database.

Detecting and handling affinity breaks in web applications

A data processing system for vector processing having a main memory accessible in parallel by a plurality of processors, each processor having a cache memory, wherein, in response to a storage instruction given to the main memory by a processor, a main memory block of a given size (BS) and having a give start address (B) and containing element data spaced at an interelement distance (D) being preempted as a result of the storage instruction, a single block address invalidation takes place at each cache memory previously having data stored at that main memory location, the single block address invalidation corresponding to (BS/D) cache address invalidations, whereby repeated sequential individual cache address invalidation operations for each address in the preeempted block no longer are required.

Hiroyuki Nishimura

Papers

Data processing system for vector processing having a cache invalidation control unit