In a disclosed PLL circuit, a constant voltage output by a constant voltage power supply 6 for obtaining a signal with a frequency equivalent to that obtained in a synchronized state is added to a signal output by a filter 3 by means of an adder 7 A signal output by the adder 7 representing the sum of the voltage output by the constant-voltage power supply and the signal output by the filter is supplied to a voltage-controlled oscillator 4 With a reference signal Pi supplied, the PLL circuit functions like an ordinary PLL circuit When the signal Pi becomes unavailable, however, a signal output by a reference-signal-input detecting circuit 5 for monitoring the reference signal Pi puts integrating components employed by the filter 3 in a short-circuit state, initializing information accumulated in the integrating components In addition, the output of the filter is set to zero In this state, only the constant voltage output by the constant-voltage power supply 6 is therefore supplied to the voltage-controlled oscillator 4

Phase locked loop circuit

PURPOSE:To shorten the time required for re-pull-in from out of locking by controlling a switch circuit in accordance with an amplitude level of an input signal and connecting a low-pass filter and a voltage oscillator, or connecting a voltage source and the voltage control oscillator. CONSTITUTION:An input signal inputted to an input terminal 11 is inputted to a phase comparator 2 and a detecting circuit 6, and the detecting circuit 6 detects an amplitude level of the input signal, and applies a control signal corresponding to its level to a switch 7 provided between a low-pass filter(LPF) 4 and a voltage controlled oscillator(VCO) 1. The switch 7 is controlled so that when the amplitude level exceeds a prescribed level, the LPF 4 and the VCO 1 are connected, and when the amplitude level is below the prescribed level, a variable voltage source 5 and the VCO 1 are connected. In such a way, a lock range of re-pull-in comes to roughly equal on the upper side and the lower side, and also, its characteristic can be set to almost the same characteristic. Moreover, even in case of an amplification level of the input signal is unstable, the time required for re-pull-in can be shortened.

A turbocharger is provided with a valve body which is disposed in a suction flow path leading from an inflow port of a housing covering a turbine rotor blade to a scroll portion and composed of a single piece or multiple divided pieces to supply a fluid to the turbine rotor blade with the inner surface thereof formed using a first wall surface and a second wall surface facing the first wall surface as part thereof, extends from the upstream side to the downstream side of the flow of the fluid, is rotatably provided in the housing in a direction toward and away from the first wall surface and the second wall surface, forms an upstream-side narrowed flow path with the first wall surface therebetween at an end on the upstream side, and forms a downstream-side narrowed flow path with the second wall surface therebetween at an end on the downstream side. The valve body has a first surface at the end on the upstream side, which faces the first wall surface, gradually approaches the first wall surface from the upstream side to the downstream side and thereafter gradually goes away therefrom, and a second surface which faces the second wall surface.

On-off valve device and rotary machine

PURPOSE:To ensure the network synchronization against clock interruption from a clock supply device by applying switching control to a switching means in a predetermined priority according to the result of detection of a clock detection means detecting the presence of a clock input of an external clock input terminal. CONSTITUTION:The equipment is provided with clock generating sections 21, 22 generating a network synchronizing clock by an output of a phase locked loop(PLL), a means outputting interruption of clock input with the highest priority, a means inputting the output of input interruption of other network synchronizing equipment, and a means changing the switching priority of the switches 11, 12 based on the input interruption of the highest priority clock of plural network synchronizing equipments. Then the network synchronizing clock output is given to a clock input terminal of the other network synchronizing equipment not with highest priority. Thus, if the clock supply equipment is interrupted or two clock paths are both broken, the redundant clock of two systems synchronized with each other is outputted.

Network synchronizing equipment and network synchronizing method

PURPOSE:To attain communication similarly to the case without a fault by generating an operating clock whose phase is synchronized with a reference clock component included in an input data signal even when a reference clock is interrupted due to a fault of a clock distribution line and when the input data signal is synchronized with the reference clock. CONSTITUTION:The changeover circuit is provided with an interruption detection section 25 detecting the presence of a reference clock from a 1st clock distribution line 1A and a selector 28 which selects a reference clock when the detection section 25 detects the presence of the reference clock and selects an extraction clock 21A in a 1st subordinate synchronizing device 2 when the absence of the reference clock is detected. Moreover, a PLL 29 is provided, which receives an output of the selector 28 and outputs an operating clock of the device 2. Then when the reference clock from the distribution line 1A exists, the PLL 29 is phase-locked with the reference clock and when no reference clock from the distribution line 1A exists, the PLL 29 is phase-locked with the reference clock. Thus, even when the clock distribution line 1A is interrupted and the reference clock from the reference clock source 1 is not supplied, the communication is ensured.

Reference clock changeover circuit for subordinate synchronization device

PURPOSE: To attian the synchronizing control of an equipment connected always to a communication system by detecting the absence of a network synchronization clock so as to apply a prescribed fixed voltage to a clock source, thereby generating the clock internally. CONSTITUTION: The network synchronizing clock and a feedback clock from a clock source 101 are subjected to phase comparison by a phase comparing means 102, a control voltage from the means 102 is supplied to output a clock synchronously with the network synchronizing clock from the clock source 101. On the other hand, when the absence of the network synchronizing clock is detected by an input interruption detection circuit 103, a changeover means 104 selects a fixed voltage similar to the control voltage from the means 102 generated from the clock source 101 to supply the clock synchronously with the network synchronizing clock to the clock source 101. Thus, even when the network synchronizing clock is absent, the synchronizing clock is generated synchronously with the network synchronizing clock in the inside of the equipment and the equipment connected to the communication system is subjected to excellent synchronization control at all times. COPYRIGHT: (C)1988,JPO&Japio

Hiroyuki Saito

Papers

Clock control system for network synchronization