An integrated circuit (20) configures the active level of an input, output, or input/output pin by sensing a logic state on the pin's bonding pad (21) at the inactivation of a reset signal, such as a power-on reset signal. The integrated circuit (20) selects a true or complement signal to provide to or from an internal circuit (25). The voltage level on the pin is latched on the active-to-inactive transition of the power-on reset signal. Thus, the use of proper board-level termination resistors (70, 71) programs the pins to the desired active logic level without the need for additional logic circuitry or a dedicated device pin.

Integrated circuit with an active-level configurable pin and method therefor.

A multi-bit latch transceiver is designed to meet the IEEE 1194.1 standard for backplane transceiver logic as specified in the IEEE 896.2 Futurebus+ specification. The latch transceiver features support for live insertion, low skew, controlled rise/fall time (2ns-5ns) and glitch free power-up/down protection. The transceiver utilizes on-chip latches and a built-in bandgap reference that provides very accurate thresholds. Unique slave stage logic in the transceiver's driver stage provides preset input conditions to the slave latch such that data is instantly clocked to the driver output when the driver is enabled, thus reducing propagation delay.

High speed, master/slave latch transceiver having a directly-driven slave stage

An integrated circuit, D-type master-slave flipflop includes a bistable master element connected between two supply voltage terminals and having a first data input for receiving data. A control means is provided having a control signal input for erasing or writing into the master element under the control of a control signal. A bistable slave element is connected between the two supply voltage terminals and has a second data input connected to a data output of the master element. The slave element is directly controlled by signals on the second data input for enabling writing into the slave element after an output signal at the master element data output reaches a predetermined voltage level.

IC D-type master/slave flip-flop

of EP0401865A VSLI circuit includes a plurality of state device circuits on a VLSI chip. Each of the state device circuits includes a latch and is clocked by a pulse generator circuit which produces narrow pulses that are coupled to the clock input of the latch. The narrow pulses have a pulse width substantially equivalent to the propagation delay through the latch of the state device circuits. By taking advantage of the high correlative percentages of devices on portions of the chip, master-slave flip flops can be implemented using only a single latch with a pulse generator.

VLSI circuit with latches controlled by a neighbouring matched clock generator

Two separate receivers (120,122) receive the input signal (128) and the clock signal (126). During the inactive state of the clock signal, the first receiver produces a low state output (130) and the second receiver produces a high state output (132). Both outputs feed combinational logic (124), which produces two outputs (142,144) both normally low. Upon transition of the clock signal, the output of only one of the receivers changes state to match the logic state of the input signal. The output of the other receiver maintains its logic state. Upon the change in the clock signal, only one of the combinational logic outputs changes state to a logical high state to indicate the state of the one input signal.

Dual receiver edge-triggered digital signal level detection system

A flip-flop arrangement receiving a clock signal and an input data and outputting a logical output in accordance with a logical level of the data. The arrangement includes a master flip-flop for transmitting a change in the logical level of the data to a pair of output ends when the clock signal is at a predetermined logical level; a slave flip-flop for latching the data transmitted via the pair of output ends; an output buffer for effecting a buffering of the data latched in the slave flip-flop; and a drive circuit for driving the output buffer. The drive circuit responds to logical levels of data appearing at the pair of output ends of the master flip-flop and, based on the logical levels, drives the output buffer to determine a logical output to be output from the arrangement, thereby reducing a total propagation delay time and realizing a high speed operation without increasing a power dissipation.

Delay type flip-flop arrangement using transistor transistor logic

A delay type flip-flop arrangement using transistor-transistor logic receives a clock signal (CP) and input data (D) and outputs a logical output (Q) in accordance with the logic level of the data. The arrangement includes a master flip-flop (1) for transmitting a change in the logic level of the data to a pair of output ends (N1, N1) when the clock signal is at a predetermined logic level; a slave flip-flop (2) for latching the data transmitted via the pair of output ends; an output buffer (3) for effecting a buffering of the data latched in the slave flip-flop; and a drive circuit (4) for driving the output buffer. The drive circuit responds to logic levels of data (Q1, Q1) appearing at the pair of output ends of the master flip-flop and, based on the logic levels, drives the output buffer to determine the logic output (Q) to be output from the arrangement. This reduces the total propagation delay time and realises a high speed operation without increasing the power dissipation.

Hitoshi Saitoh

Papers

Delay type flip-flop arrangement using transistor transistor logic

A flip-flop arrangement.