A clock generator having a delay locked loop and a duty cycle correction circuit. The delay locked loop adjusts a first adjustable delay circuit to generate a first output clock signal that is synchronized with a first input clock signal and adjusts a second adjustable delay circuit to provide a delay that is equal to the first adjustable delay circuit. A duty cycle correction circuit is coupled to the first and second inputs of the delay locked loop and further coupled to the second adjustable delay circuit. The duty cycle correction circuit is configured to determine a duty cycle error of at least one of the first and second input clock signals and adjust the second adjustable delay circuit to provide a corrected delay compensating for the duty cycle error.

Clock generator having a delay locked loop and duty cycle correction circuit in a parallel configuration

Memories, multi-phase clock signal generators, and methods for generating multi-phase duty cycle corrected clock signals are disclosed. For example, one such clock signal generator includes a delay-locked loop having a first multi-tap adjustable delay line configured to delay a reference signal to provide a plurality of clock signals having different phases relative to the reference clock signal. A periodic signal generated by the delay-locked loop is provided to a second multi-tap adjustable delay line as an input clock signal. Clock signals from taps of the second multi-tap adjustable delay line are provided as the multi-phase duty cycle corrected clock signals.

Multi-phase duty-cycle corrected clock signal generator and memory having same

A system and method for generating a correction signal for correcting duty cycle error of a first clock signal relative to a second complementary clock signal. Changes to a time difference between high- and low-portions of the first clock signal are detected and the correction signal is generated in response to and accordance with the detected changes.

Duty cycle error calculation circuit for a clock generator having a delay locked loop and duty cycle correction circuit

The present invention relates to a duty cycle correction circuit of a DLL circuit. According to the present invention, in an Active Power-Down Mode (APDM), a voltage comparator of a duty cycle correction circuit operates without being reset. Therefore, although an internal power supply voltage is instantly changed in the APDM, the duty cycle of a DLL clock can be accurately set to 50%.

Duty cycle correction circuit of a DLL circuit

Methods and arrangements to adjust a duty cycle of a clock signal are disclosed. Embodiments may include a duty cycle controller to adjust the duty cycle of the clock signal based upon a delay signal and an input clock signal. A duty cycle detector may determine signals with frequencies based upon the duty cycle of the output signal and a correction module may compare the frequencies of the detector signals to generate the delay signal. In some embodiments, once the duty cycle of the output clock signal reaches the desired duty cycle such as fifty percent, the correction module may be turned off.

Methods and arrangements to adjust a duty cycle

Provided is a digital duty cycle correction circuit and method for a multi-phase clock, in which duty cycle correction information of an input clock signal is stored in a power save state of a system by adopting a digital correction method in a duty cycle correction method for a multi-phase clock and phase information of the input clock signal is held constant during duty cycle correction of the input clock signal by correcting duty cycles of the input clock signal by changing the falling edge of the clock without changing the rising edge of the input clock signal during duty cycle correction of the input clock signal, thereby correcting the multi-phase clock. To this end, the digital duty cycle correction circuit includes a clock delay means that takes the form of a shunt capacitor-inverter, a clock generation means including a clock rising edge generation circuit and a clock falling edge generation circuit, and a digital duty cycle detection means including integrators, a comparator, and a counter/register.

Digital duty cycle correction circuit and method for multi-phase clock

A bubble error rejecter includes a cascade of front and rear voting sections for correcting bubble errors spanning multiple bits from interpolation. The front voting section generates first correction codes from first thermometer codes determined from preamplified signals. The rear voting section generates second correction codes from the first correction codes and second thermometer codes determined from interpolation of the preamplified signals.

Bubble error rejecter in data converter

A duty cycle correction circuit is operated by maintaining a state of a duty cycle corrected signal, generating a first transition in the state of the duty cycle corrected signal responsive to an input signal, and generating a second transition in the state of the duty cycle corrected signal responsive to a delayed version of the input signal.

Duty cycle correction circuits including a transition generator circuit for generating transitions in a duty cycle corrected signal responsive to an input signal and a delayed version of the input signal and methods of operating the same

PURPOSE: A circuit for correcting the digital duty cycle for a multi-phase clock and a method for the same are provided to correct the duty cycle of the overall clock by changing the falling edge of the clock without changing the rising edge of the clock. CONSTITUTION: A circuit for correcting the digital duty cycle for a multi-phase clock includes a rising clock generating unit(120), a falling clock generating unit(130) and a clock delay unit(140). The rising clock generating unit detects the rising edge of the inputted clock and generates the rising edge of the duty cycle correction clock. The falling clock generating unit detects the rising edge of the clock with 180 degrees shift from the inputted clock and generates the falling edge of the duty cycle correction clock. And, the clock delay unit inputs the inputted clock with 180 degree shift into the falling clock generating unit.

Circuit for correcting digital duty cycle for multi-phase clock and method for the same, especially not depending on duty cycle of input clock

Delay locked loop (DLL) circuits have a phase detector circuit that can detect a phase difference between an input clock signal and an output clock signal over a time period of 0T-2T. The delay applied to generate the output signal is adjusted based on the detected phase difference. A middle clock signal can be generated that has a phase that is between the input clock signal and the output clock signal. The phase detector circuit may be configured to detect the phase difference between the input clock signal and the output clock signal over the time period 0T-2T responsive to the middle clock signal.

Hong-June Park

Papers

Digital duty cycle correction circuit and method for multi-phase clock

Bubble error rejecter in data converter

Duty cycle correction circuits including a transition generator circuit for generating transitions in a duty cycle corrected signal responsive to an input signal and a delayed version of the input signal and methods of operating the same

Circuit for correcting digital duty cycle for multi-phase clock and method for the same, especially not depending on duty cycle of input clock

Delay locked loop (dll) circuits having an expanded operation range and methods of operating the same