System level synthesis is widely seen as the solution for closing the productivity gap in system design. High level system models are used in system level design for early design exploration. While real time operating systems (RTOS) are an increasingly important component in system design, specific RTOS implementations can not be used directly in high level models. On the other hand, existing system level design languages (SLDL) lack support for RTOS modeling. In this paper we propose a RTOS model built on top of existing SLDLs which, by providing the key features typically available in any RTOS, allows the designer to model the dynamic behavior of multi-tasking systems at higher abstraction levels to be incorporated into existing design flows. Experimental result shows that our RTOS model is easy to use and efficient while being able to provide accurate results.

/pdf/rtos-modeling-for-system-level-design-526fqrz2so.pdf

RTOS Modeling for System Level Design

SystemC is committed to support the requirements for an integrated, HW/SW co-design flow, thus allowing the development of complex, multiprocessing, Systems-on Chip (MpSoC). To make this possible, efficient modeling and simulation methodologies for Real-Time, Embedded (RT/E) SW in SystemC have to be developed, so that the designer can verify and refine the application SW together with the rest of the elements of the platform. Accurate modeling of the application SW requires an accurate model of the RTOS. Nevertheless, low-level, dynamic timing characteristics of the RTOS such as time-slicing, priority-based preemptive scheduling, interrupts and exceptions do not have a direct implementation in SystemC.

In this paper, techniques are proposed to accurately model the detailed RTOS functionality on top of the SystemC execution kernel. The model allows timed-simulation and refinement of the RT/E SW code in SystemC. The simulation technology has been applied to the development of a high-level, POSIX simulation library in SystemC. The library allows the designer a fast, sufficiently accurate, timed simulation of the application SW running on top of POSIX. As most current RTOSs support this standard, the library is portable to different development frameworks. The library provides the required infrastructure for a complete, multiprocessing, HW/SW co-simulation environment at different abstraction levels using SystemC.

RTOS modeling in SystemC for real-time embedded SW simulation: A POSIX model

With the increasing SW content of modern SoC designs, modeling and development of Hardware Dependent Software (HDS) become critical. Previous work addressed this by introducing abstract RTOS modeling [6], which exposes dynamic scheduling effects early in the system design flow. However, such models insufficiently capture preemption. In particular, the accuracy of preemption depends on the granularity of the timing annotation. For an accurately modeled interrupt response time, very fine-grained timing annotation is necessary, which contradicts the RTOS abstraction idea and is detrimental to simulation performance.In this paper, we eliminate the granularity dependency by applying the Result Oriented Modeling (ROM) technique previously used only for communication modeling. Our ROM approach allows precise preemptive scheduling, while retaining all the benefits of abstract RTOS modeling. Our experimental results demonstrate tremendous improvements. While the traditional model simulated an interrupt response time with a severe inaccuracy (12x longer in average and 40x longer for 96th percentile), our ROM-based model was accurate within 8% (average and 50th percentile) using identical timing annotations.

/pdf/introducing-preemptive-scheduling-in-abstract-rtos-models-1uio085wpm.pdf

Introducing preemptive scheduling in abstract RTOS models using result oriented modeling

This paper presents an RTOS-centric hardware/software cosimulator which we have developed for embedded system design. One of the most remarkable features in our cosimulator is that it has a complete simulation model of an RTOS which is widely used in industry, so that application tasks including RTOS service calls are natively executed on a host computer. Our cosimulator also features cosimulation with functional simulation models of hardware written in C/C++ and cosimulation with HDL simulators. A case study with a JPEG decoder application demonstrates the effectiveness of our cosimulator.

RTOS-centric hardware/software cosimulator for embedded system design

Raising the level of abstraction in system design promises to enable faster exploration of the design space at early stages. While scheduling decision for embedded software has great impact on system performance, it's much desired that the designer can select the right scheduling algorithm at high abstraction levels so as to save him from the error-prone and time consuming task of tuning code delays or task priority assignments at the final stage of system design. In this paper we tackle this problem by introducing a RTOS model and an approach to refine any unscheduled transaction level model (TLM) to a TLM with RTOS scheduling support. The refinement process provides a useful tool to the system designer to quickly evaluate different dynamic scheduling algorithms and make the optimal choice at the early stage of system design.

/pdf/rtos-scheduling-in-transaction-level-models-4x7qxw5nfh.pdf

RTOS scheduling in transaction level models

Many real-world embedded systems employ a preemptive scheduling policy in order to satisfy their realtime requirements. However, most System-Level Design Languages (SLDLs) which were proposed up to now, such as SpecC, do not explicitly support modeling of preemptions. This paper proposes techniques for modeling xed-priority preemptive multi-task systems in the SpecC SLDL. The modeling techniques with SpecC enable a system designer to specify and simulate preemptive multi-task systems including both software and hardware at a high level of abstraction, without assuming any speci c real-time operating system.

Modeling Fixed-Priority Preemptive Multi-Task Systems in SpecC

Advances in semiconductor technology and increased reusability of IPs enable embedded system designers to develop Systems-On-Chip (SOCs) which are customized for a speci c application (or application domain). Speci cally, customization of processor architecture and memories is enabled, which allows e cient implementation of SOCs. Up to now, a number of research e orts on processor customization have been made in both industry and academia, where the instruction set and the datapath con guration are prime design parameters. In this paper we demonstrate that the datapath bitwidth has a large impact on system performance, chip area, and energy consumption, and then propose a framework and tools for datapath bitwidth optimization. Two case studies are presented to prove the e ectiveness of the optimization.

A Framework for Bitwidth Optimization in System-on-Chip Design

Power consumption has been a critical issue in the embedded system design. However, embedded software has been traditionally designed without taking care of the power consumption issues. This paper addresses several software techniques for reducing the power consumption and discusses their importance in the embedded system design.

Software Techniques for Low Power Embedded Systems

Scratch-pad memories (SPM) are on-chip memory devices which are much smaller but much faster and which consume much less energy than off-chip memories. This paper presents two fully software techniques for respectively sharing the SPM among several tasks and managing the stacks of each task between the SPM and the external main memory (MM). The paper then explains then how to merge efficiently these techniques for achieving further energy consumption reduction.

宏之冨山

Papers

Modeling Fixed-Priority Preemptive Multi-Task Systems in SpecC

A Framework for Bitwidth Optimization in System-on-Chip Design

Software Techniques for Low Power Embedded Systems

Placing Static and Stack Data into a Scratch-Pad Memory for Reducing the Energy Consumption of Multi-task Applications

宏之 冨山

Papers

Modeling Fixed-Priority Preemptive Multi-Task Systems in SpecC

A Framework for Bitwidth Optimization in System-on-Chip Design

Software Techniques for Low Power Embedded Systems

Placing Static and Stack Data into a Scratch-Pad Memory for Reducing the Energy Consumption of Multi-task Applications

宏之冨山