A method and system for decoding low density parity check (“LDPC”) codes. An LDPC decoder includes an R select unit, a Q message first-in first-out (“FIFO”) memory, and a cyclic shifter. The R select unit provides an R message by selecting from a plurality of possible R message values. The Q message memory stores a Q message until an R message is generated by a CNU, the Q message and the R message are combined to provide a P message. The cyclic shifter shifts the P message.

Low density parity check decoder for regular LDPC codes

By implementing a field-programmable gate array (FPGA)-based simulator, we investigate the performance of randomly constructed high-rate quasi-cyclic (QC) low-density parity-check (LDPC) codes for the magnetic recording channel at very low block sector error rates. On the basis of extensive simulations, we conjecture guidelines for designing randomly constructed high-rate regular QC-LDPC codes with low error floor for the magnetic recording channel. Experimental results show that our high-rate regular QC-LDPC codes do not suffer from error floor, at least at block error rates of 10-9, and can realize significant coding gains over Reed-Solomon codes that are used in current practice. Furthermore, we develop a QC-LDPC decoder hardware architecture that is well suited to achieving high decoding throughput. Finally, to evaluate the implementation feasibility of LDPC codes for the magnetic recording channel, using 0.13 mum standard cell and memory libraries, we designed a read channel signal processing datapath consisting of a parallel max-log-MAP detector and a QC-LDPC decoder, which can achieve a throughput up to 1.8 Gb/s

Quasi-Cyclic LDPC Codes for the Magnetic Recording Channel: Code Design and VLSI Implementation

Many classes of high-performance low-density parity-check (LDPC) codes are based on parity check matrices composed of permutation submatrices. We describe the design of a parallel-serial decoder architecture that can be used to map any LDPC code with such a structure to a hardware emulation platform. High-throughput emulation allows for the exploration of the low bit-error rate (BER) region and provides statistics of the error traces, which illuminate the causes of the error floors of the (2048, 1723) Reed-Solomon based LDPC (RS-LDPC) code and the (2209, 1978) array-based LDPC code. Two classes of error events are observed: oscillatory behavior and convergence to a class of non-codewords, termed absorbing sets. The influence of absorbing sets can be exacerbated by message quantization and decoder implementation. In particular, quantization and the log-tanh function approximation in sum-product decoders strongly affect which absorbing sets dominate in the errorfloor region. We show that conventional sum-product decoder implementations of the (2209, 1978) array-based LDPC code allow low-weight absorbing sets to have a strong effect, and, as a result, elevate the error floor. Dually-quantized sum-product decoders and approximate sum-product decoders alleviate the effects of low-weight absorbing sets, thereby lowering the error floor.

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Design of LDPC decoders for improved low error rate performance: quantization and algorithm choices

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Design of LDPC Decoders for Improved Low Error Rate Performance

Several high performance LDPC codes have parity-check matrices composed of permutation submatrices. We design a parallel-serial architecture to map the decoder of any structured LDPC code in this large family to a hardware emulation platform. A peak throughput of 240 Mb/s is achieved in decoding the (2048,1723) Reed-Solomon based LDPC (RS-LDPC) code. Experiments in the low bit error rate (BER) region provide statistics of the error traces, which are used to investigate the causes of the error floor. In a low precision implementation, the error floors are dominated by the fixed-point decoding effects, whereas in a higher precision implementation the errors are attributed to special configurations within the code, whose effect is exacerbated in a fixed-point decoder. This new characterization leads to an improved decoding strategy and higher performance.

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GEN03-6: Investigation of Error Floors of Structured Low-Density Parity-Check Codes by Hardware Emulation

In this paper, we present a general approach for constructing high-rate cycle codes having girth 12 which achieve the lower bound on the block length. An efficient encoding algorithm is also proposed for this class of codes. We estimate the word error rate of the cycle codes for additive white Gaussian noise (AWGN) channels under maximum likelihood decoding, using the minimum distance and its multiplicity. These estimates are compared to simulation results with iterative soft decoding. The performance of these codes for partial response channels is studied under iterative soft decoding using computer simulations.

Large girth cycle codes for partial response channels

Iterative codes such as low density parity check (LDPC) codes and turbo product codes (TPC) are of interest for data storage applications To apply these codes to digital recording systems, two possible schemes are considered in this paper In the first scheme, a single LDPC code of column weight j>2 is used to replace the Reed-Solomon (RS) code of the conventional channel In the second scheme, an iterative code is used as the inner code and is concatenated with an outer RS code Single parity check TPC code is considered for this scheme We developed a high-throughput field programmable gate array (FPGA) platform to evaluate the error floor performance of LDPC codes and the error statistics of TPC codes in partial response (PR) channel with turbo equalization High rate codes (rate 8/9 for LDPC code and rate 0935 for TPC code) are evaluated for magnetic recoding application The bit error rate (BER) performance of LDPC code down to 10/sup -10/ can be reached within 2 h using the FPGA platform The TPC code error statistics are evaluated using about 10/sup 11/ bits at different signal-to-noise (SNR) levels For practical implementation complexity and power consumption, 2 channel iterations and 2 TPC decoder iterations are employed The results show that the gain by applying TPC code under 2 channel iterations and 2 TPC decoder iterations is marginal

Field programmable gate array (FPGA) for iterative code evaluation

Low density parity check (LDPC) codes have shown 3 to 5 dB coding gain, at bit error rates (BER) around 10/sup -5/, over the uncoded partial response maximum-likelihood (PRML) channels. However, the error floor of LDPC codes is still an open question and is one of the major concerns in applying LDPC codes in high density receding channel. Due to the suboptimal nature of decoding schemes and the difficulties in code spectrum analysis, the performance analysis of LDPC code at very low BER region is very difficult, if not impossible. Therefore, the performance of LDPC codes is usually evaluated through Monte Carlo simulations. The sequential nature of the conventional C simulations limits their capability for BER investigation. It takes months to evaluate the performance of codes in partial response (PR) channel at 10/sup -9/ BER using optimized C code and a 2 GHz computer. To investigate the error floors, a high-throughput, fully-reconfigurable field programmable gate array (FPGA) platform was developed for the evaluation of LDPC codes in PR channel. In this paper, the architecture, main features and throughput of the channel simulator on FPGA was described. The error floor of one type of LDPC code is shown as an example.

Field programmable gate array-based investigation of the error floor of low density parity check (LDPC) codes for magnetic recording channel

A pseudo-random bit interleaver and de-interleaver comprising a source for generating pseudo-random numbers and transformation logic that transforms each pseudo-random number generated by the source into a plurality of different pseudo-random numbers. Each of the transformed pseudo-random numbers identifying a parity equation to which an incoming bit will be assigned for computing parity.

Method and apparatus for encoding and decoding data using a pseudo-random interleaver

Methods and apparatus are provided for programmable codeword encoding and decoding. Data blocks are represented as a number of codewords. Data is encoded into one or more full size codewords and at least one truncated codewords. Typically, data is encoded and decoded using one or more full size codewords and one truncated codeword. The truncated codewords are a two-dimensional array having a number of columns (or rows or both) less than the full size codeword. In this manner, the disclosed truncated codewords are adaptable to various system parameters that affect code rate.

Hongwei Song

Papers

Large girth cycle codes for partial response channels

Field programmable gate array (FPGA) for iterative code evaluation

Field programmable gate array-based investigation of the error floor of low density parity check (LDPC) codes for magnetic recording channel

Method and apparatus for encoding and decoding data using a pseudo-random interleaver

Method and apparatus for programmable codeword encoding and decoding using truncated codewords