Method and structures are provided for conformal capacitor dielectrics over textured silicon electrodes for integrated memory cells. Capacitor structures and first electrodes or plates are formed above or within semiconductor substrates. The first electrodes include hemispherical grain (HSG) silicon for increasing the capacitor plate surface area. The HSG topography is then exposed to alternating chemistries to form monolayers of a desired dielectric material. Exemplary process flows include alternately pulsed metal organic and oxygen source gases injected into a constant carrier flow. Self-terminated metal layers are thus reacted with oxygen. Near perfect step coverage allows minimal thickness for a capacitor dielectric, given leakage concerns for particular materials, thereby maximizing the capacitance for the memory cell and increasing cell reliability for a given memory cell design. Alternately pulsed chemistries are also provided for depositing top electrode materials with continuous coverage of capacitor dielectric, realizing the full capacitance benefits of the underlying textured morphology.

Conformal thin films over textured capacitor electrodes

An integrated circuit and fabrication method includes a memory cell for a dynamic random access memory (DRAM). Vertically oriented access transistors are formed on semiconductor pillars on buried bit lines. Buried first and second gates are provided for each access transistor on opposing sides of the pillars. Buried word lines extend in trenches orthogonal to the bit lines. The buried word lines interconnect ones of the first and second gates. In one embodiment, unitary gates are interposed and shared between adjacent pillars for gating the transistors therein. In another embodiment, separate split gates are interposed between and provided to the adjacent pillars for separately gating the transistors therein. In one embodiment, the memory cell has a surface area that is approximately 4 F 2 , where F is a minimum feature size. Bulk-semiconductor and semiconductor-on-insulator (SOI) embodiments are provided.

Memory cell having a vertical transistor with buried source/drain and dual gates

A memory cell structure for a folded bit line memory array of a dynamic random access memory device includes buried bit and word lines, with the access transistors being formed as a vertical structure on the bit lines. Isolation trenches extend orthogonally to the bit lines between the access transistors of adjacent memory cells, and a pair of word lines are located in each of the isolation trenches. The word lines are oriented vertically widthwise in the trench and are adapted to gate alternate access transistors, so that both an active and a passing word line can be contained within each memory cell to provide a folded bit line architecture. The memory cell has a surface area that is approximately 4 F2, where F is a minimum feature size. Also disclosed are processes for fabricating the DRAM cell using bulk silicon or a silicon on insulator processing techniques.

4 F2 folded bit line dram cell structure having buried bit and word lines

The present invention includes a method for bonding one semiconductor surface to a second semiconductor surface. The method includes providing a first article that has a semiconductor surface and a second article that has a semiconductor surface. The semiconductor surfaces are annealed with an energy source wherein energy is confined to the semiconductor surfaces. The annealed surfaces are bonded to each other.

Low temperature silicon wafer bond process with bulk material bond strength

A high density flash EEPROM provides increased nonvolatile storage capacity. A memory cell array includes densely packed memory cells, each cell having a semiconductor pillar providing shared source/drain regions for two vertical floating gate transistors that have individual floating and control gates distributed on opposing sides of the pillar. The control gates are formed together with interconnecting gate lines. First source/drain terminals are row addressable by interconnection lines disposed substantially orthogonal to the gate lines. Second source/drain terminals are column addressable by data lines disposed substantially parallel to the gate lines. Both bulk semiconductor and silicon-on-insulator embodiments are provided. If a floating gate transistor is used to store a single bit of data, an area of only 2F 2 is needed per bit of data, where F is the minimum lithographic feature size. If multiple charge states (more than two) are used, an area of less than 2F 2 is needed per bit of data.

High density flash memory

This HSG-Si cylindrical capacitor structure achieves a cell capacitance of 30 fF with 04 mu m-high storage electrode in a 072 mu m/sup 2/ cell area A new selective etching technique using a low-pressure vapor hydrogen fluoride is developed to form the cylindrical capacitor electrode The high selective etching (2000 times) of borophosphosilicate-glass to SiO/sub 2/ is realized Disilane molecule irradiation in ultra-high vacuum chamber achieves the HSG-Si formation on the whole surface of phosphorous doped amorphous Si cylindrical electrode >

A new cylindrical capacitor using hemispherical grained Si (HSG-Si) for 256Mb DRAMs

Introduction In the down-scaling of DRAM cells, an advanced storage capacitor structure is required to provide sufficiently large Capacitance in a limited area, and enlargement of the surface of storage electrodes is one of the most effective approaches to meeting this requirement[ 1-31. One recent approach to enhance surface area has been the development of hemispherical grained (HSG) Si, whose grain size can be controlled from 30 to 100 nm, on the storage tlectrode[4-71. This is an effective technique for surface area enlargement. However, the surface area enlargement ratio of HSG-Si electrode is at most two times as large as that of conventioml stacked capacitor. It is considered that formation of micro roughness on the HSG-Si surface can realize the additional increase of electrode surface area. In the present work, we have developed a new technique, in which a phosphorous (P) doped poly-Si is changed into a porousSi through H,PO, solution treatment. By using this technique, surface of stacked electrodes can be entirely covered with micro cavities, and their surface area are effectively increased. 3.4 times storage capacitance can be obtained with the micro cavity covered HSG-Si simple structured electrode.

http://ieeexplore.ieee.org/iel4/6147/16441/00760223.pdf

Honma

Papers

A new cylindrical capacitor using hemispherical grained Si (HSG-Si) for 256Mb DRAMs

A Novel Stacked Capacitor With Porous-Si Electrodes For High Density DRAMs