In a data processing system having a first external memory, a second external memory, and a control memory for storing information on data renewals in the first external memory, a system and a method provide for back-up operations in parallel with ordinary data processing, including dump processing in which renewed data parts in the first external memory are copied as backup data into the second external memory with reference to the contents of the control memory. The method provides the step of storing into the control memory first identifier information for identifying areas of the first external memory where data items were renewed; the step of storing into the control memory second identifier information for identifying areas of the first external memory where data items were renewed during the dump processing; and the step of erasing at completion of the dump processing the first identifier information items except those which identify the same areas as identified by the second identifier information items. Thus, ordinary job processing and the renewals of the data items of the first external memory can be performed even in the course of the data dumping processing.

Backup control method and system in data processing system using identifiers for controlling block data transfer

A disk storage subsystem includes both volatile and non-volatile portions of memory. In response to a write command from a host computer, the controller allocates a predetermined number of memory blocks in the non-volatile cache memory and allocates a corresponding number of blocks in the volatile memory. Host supplied write data is then stored in the allocated non-volatile memory blocks. The data may also be mirrored in additional non-volatile memory. Immediately thereafter the subsystem sends an acknowledge signal to the host. The subsystem then performs a DMA operation to copy the write-data from the non-volatile memory blocks to the volatile memory blocks. The write-data is then stored on a disk drive at which point the non-volatile memory may be de-allocated. Subsequent reads of the given data may be read from the volatile memory, reducing disk access time. In the event of a power failure, data stored in the non-volatile memory but not yet written to disk is preserved. In the event of a disk controller failure, the non-volatile memory modules may be transferred to a functioning disk controller for recovery.

Disk controller with volatile and non-volatile cache memories

Disclosed is a multiprocessor computer system including a plurality of processor modules with each of the processor modules including at least one processor and a cache memory which is shared by all of the processors of each processor module. The processor modules are connected to a system bus which comprises independent data, address, vectored interrupt, and control buses. A system memory which is shared by all the processor modules is also connected to the buses, and the cache memories in each processor module store those memory locations in the main memory most frequently accessed by the processors in its module. A system control module controls the operation and interaction of all of the modules and contains the bus arbiters for the vector, data and address buses. The system control module also controls the retrying of requests which are not completed and should any requester fail to obtain access to a bus, the system control module also unjams this deadlock. Each of these multiprocessor computer systems can be connected to another multiprocessor computer system through an interface which includes a cache for housing frequently accessed locations of the other multiprocessor system.

Multiprocessor computer system employing a plurality of tightly coupled processors with interrupt vector bus

A type of search engine (referred to as the “Get Engine”) receives one or more keywords, semantically formulates a question being asked from the keywords, generates specifications for the query, and searches a website index to determine websites that are likely owners of the answer to the question based on the query specifications and website classifications. The Get Engine determines a website that is most likely the owner of the answer based on credibility, searches the pages of the website using the keywords and additional keywords related to the query, retrieves the answer from the pages of the website, and receives feedback used in part to determine the credibility of the website.

Providing answer to keyword based query from natural owner of information

A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controller connected to address buses and control buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween. The control system further includes a data path switch connected to data buses respectively of the processor, memory, and system buses to transfer data via the data buses therebetween depending on the data path control signal.

Bus system for use with information processing apparatus

A data processing machine in which the cache operating cycle is divided into two subcycles dedicated to mutually exclusive operations. The first subcycle is dedicated to receiving a central processor memory read request, with its address. The second subcycle is dedicated to every other kind of cache operation, in particular either (a) receiving an address from a peripheral processor for checking the cache contents after a peripheral processor write to main memory, or (b) writing anything to the cache, including an invalid bit after a cache check match condition, or data after either a cache miss or a central processor write to main memory. The central processor can continue uninteruptedly to read the cache on successive central processor microinstruction cycles, regardless of the fact that the cache contents are being "simultaneously" checked, invalidated or updated after central processor writes. After a cache miss, although the central processor must be stopped to permit updating, it can resume operations a cycle earlier than is possible without the divided cache cycle.

Horace H. Tsiang

Papers

Data processing machine with improved cache memory management