Dynamic voltage restorers (DVRs) are used to protect sensitive loads from the effects of voltage sags on the distribution feeder. This paper presents and verifies a novel voltage sag detection technique for use in conjunction with the main control system of a DVR. In all cases it is necessary for the DVR control system to not only detect the start and end of a voltage sag but also to determine the sag depth and any associated phase shift. The DVR, which is placed in series with a sensitive load, must be able to respond quickly to a voltage sag if end users of sensitive equipment are to experience no voltage sags. A problem arises when fast evaluation of the sag depth and phase shift is required, as this information is normally embedded within the core of a main DVR control scheme and is not readily available to either users monitoring the state of the grid or parallel controllers. Previous research presented an additional controller, which required phase and sag depth information to manipulate the injection voltage vector returned by the main controller in order to prevent the DVR injection transformers from saturating. Typical standard information tracking or detection methods such as the Fourier transform or phase-locked loop (PLL) are too slow in returning this information, when either applied to the injection voltage vector, or to the supply voltages directly. As a result of this the voltage sag detection method in this paper proposes a new matrix method, which is able to compute the phase shift and voltage reduction of the supply voltage much quicker than the Fourier transform or a PLL. The paper also illustrates that the matrix method returns results that can be directly interpreted, whereas other methods such as the wavelet transform return results that can be difficult to interpret.

Voltage sag detection technique for a dynamic voltage restorer

This paper proposes a low-voltage ride-through technique of a doubly fed induction generator (DFIG) wind turbine system using a dynamic voltage restorer (DVR). For effective control of the DVR, digital all-pass filters are used for extracting the positive-sequence component from the unbalanced grid voltage since they have the advantages of giving a desired phase shift and no magnitude reduction over conventional low- or high-pass filters. Using the positive-sequence component, the phase angles for the positive- and negative-sequence components of the grid voltage are derived. A control algorithm for the DVR that is dual voltage controllers only is implemented for the two sequence components in the dq synchronous reference frame. In order to achieve the power rating reduction of the DVR, the stator power reference for the DFIG is reduced during faults. In addition, a control scheme of pitch angle system is applied to stabilize the operation of the wind turbine system in the event of grid faults. PSCAD/EMTDC simulations show the effectiveness of the proposed technique and a feasibility of reducing the power rating of DVR for the fault ride-through capability of DFIG. The validity of the proposed control scheme for the DVR has also been verified by experimental results.

A Fault Ride-Through Technique of DFIG Wind Turbine Systems Using Dynamic Voltage Restorers

The present invention provides a multilevel electric power converter including a plurality of DC voltage sources providing different DC source voltage levels. The DC source voltage levels are preferably multiples of each other and may vary in a binary fashion or in a geometric progression with a factor of three to provide a large number of output voltage levels for a given number of inverter levels. The multilevel inverter is preferably implemented as a series connected set of H-bridge inverters, with each H-bridge inverter having an independent DC voltage source providing the desired DC source voltage level. A hybrid modulation strategy may be employed whereby the lowest voltage level inverter is modulated at a high frequency, e.g., by pulse width modulation, and higher voltage level inverters in the multilevel inverter are modulated to provide a low frequency stepped waveform. The combined high frequency pulse width modulated and low frequency stepped waveform has good spectral quality. A high voltage high quality waveform may be generated in this manner by taking advantage of the high voltage blocking capability of switching devices, such as GTO thyristors, in the high voltage inverters in the multilevel inverter, and the high frequency switching characteristics of switching devices, such as IGBTs, in the lowest voltage level inverter in the multilevel inverter. A multilevel inverter in accordance with the present invention may be employed in a single-phase or multi-phase applications.

Hybrid topology for multilevel power conversion

A new series power conditioning system using a matrix converter with flywheel energy storage is proposed to cope with voltage sag problem. Previous studies have highlighted the importance of providing adequate energy storage in order to compensate for deep voltage sags of long durations in weak systems. With the choice of flywheel as a preferred energy storage device, the proposed solution utilizes a single ac/ac power converter for the grid interface as opposed to a more conventional ac/dc/ac converter, leading to higher power density and increased system reliability. The paper develops the dynamic model for the complete system including the matrix converter in dual synchronous reference frames coupled to the flywheel- machine and the grid, respectively. The dynamic model is used to design a vector control system that seamless integrates functions of compensating load voltage and managing energy storage during voltage sag and idling modes. The numerical simulation results and experimental results from a laboratory-scale hardware prototype are presented to verify system performance.

https://www.egr.msu.edu/~bingsen/files_publications/C-07_IAS.pdf

Dynamic Voltage Restorer Utilizing a Matrix Converter and Flywheel Energy Storage

A new multilevel inverter (MLI) topology is proposed using a level doubling network (LDN). The LDN takes the form of a half-bridge inverter to almost double the number of output voltage levels. The concept (of the proposed LDN) has the capability of self-balancing during positive and negative cycles without any closed-loop control/algorithm, and it does not consume or supply any power. The topology uses a symmetric cascaded H-bridge MLI but offers an equivalent performance of an asymmetric topology in terms of the number of levels. Also, it maintains the merit of uniform loading of the individual cell for a symmetric MLI. The topology is implemented by connecting only a three-arm H-bridge (only two switches per phase) with the entire three-phase inverter to double the number of levels. Thus, it significantly improves the power quality, reduces the switching frequency, and reduces the cost and size of the power filter. Operation of the circuit is verified by simulation result and experiments from a laboratory prototype.

A New Multilevel Inverter Topology With Self-Balancing Level Doubling Network

This paper presents the technical aspects of designing a dynamic voltage restorer to meet the stringent requirements of voltage dips mitigation with respect to the magnitude of voltage dip, fault duration, permissible line voltage deviations and response time. An introduction to IGCT technology based on latest transparent anode GTO (T-GTO) and gate technology is given. The performance of the DVR based on digital simulations is discussed. A description of a hardware-based real-time simulator model for the performance assessment of DVR in voltage dips mitigation is presented. The results of the real-time simulator are compared with the digital simulations. Finally, control and protection concepts for the DVR are highlighted.

Power supply quality improvement with a dynamic voltage restorer (DVR)

This paper presents the technical aspects of designing a Dynamic Voltage Restorer to meet the stringent requirements of voltage dips mitigation with respect to the magnitude of voltage dip, fault duration, permissible line voltage deviations and response time. An introduction to the IGCT technology based on latest transparent anode GTO (I-GTO) and gate technology is given. The performance of the DVR based on digital simulations is discussed. A description of a hardware based real time simulator model for performance assessment of DVR in voltage dips mitigation is presented. The results of the real time simulator are compared with the digital simulations. Finally, control and protection concepts for the DVR are highlighted.

http://ieeexplore.ieee.org/iel4/5223/14222/00654018.pdf

Power Supply Quality ~~provement with a Dynamic Vol ge Restorer (DVR)

A converter circuit arrangement is specified which is constructed to have a particularly low inductance. This is achieved by the circuit area of the commutation circuit being kept as small as possible. A circuit area which is as small as possible is achieved by the branch modules and switch modules of a phase module being arranged either in a U-shape or in a meandering shape. The branch modules can be arranged either parallel to or at right angles to a main direction, between the positive and negative connections and the load connection. In addition, it is advantageous if the power semiconductor switches and the reverse-connected parallel diodes and freewheeling diodes are arranged in separate stacks which are held together by means of a clamping-in device.

Converter arrangement having a low-inductance commutation circuit

In a quarter-bridge circuit for high currents the total current is subdivided into a plurality of parallel current paths. In each current path a semiconductor component (5.1, . . . , 5.n, 6.1, . . . , 6.n) that can be turned off via a gate, a freewheeling diode (7.1, . . . , 7.n, 8.1, . . . , 8.n) located opposite a midpoint, and a clamping capacitor (9.1, . . . , 9.n, 10.1, . . . , 10.n) are arranged in parallel with the freewheeling diode (7.1, . . . 7.n, 8.1, . . . , 8.n) and the turnoff semiconductor component (9.1, . . . , 9.n, 10.1, . . . , 10.n) in such a way that the respective freewheeling path has as minimal an inductance as possible. Provided between a load terminal (3) of the quarter-bridge circuit and each midpoint of a current path is one inductor (L11.1, . . . , L11.n, L21., . . . , L21.n) each which limits the rate of current rise, so that a current rush caused by an operating delay does not overload the turnoff semiconductor component (9.1, . . . , 9.n, 10.1, . . . , 10.n). Each current path is preferably realized by means of a separate module. The quarter-bridge is suitable for series connection, equally as a part of a bridge circuit or of a chopper.

Quarter bridge circuit for high currents

A power electronic circuit arrangement which comprises a first power converter is specified A second power converter is connected between the load terminals of the first power converter and a load The negative or positive values of the DC voltage intermediate circuits of the first and second power converters can be added by means of corresponding driving of the power converters This achieves finer voltage gradation and, consequently, an improved approximation of the resulting output voltage to the sinusoidal waveform

Horst Dr. Grüning

Papers

Power supply quality improvement with a dynamic voltage restorer (DVR)

Power Supply Quality ~~provement with a Dynamic Vol ge Restorer (DVR)

Converter arrangement having a low-inductance commutation circuit

Quarter bridge circuit for high currents

Power electronic circuit arrangement having plural power converters