A shape-based layout beautification operation can be performed on an IC layout to correct layout imperfections. A shape is described by edges (and vertices) related according to specified properties. Each shape can be configured to match specific layout imperfection types. Corrective actions can then be associated with the shapes, advantageously enabling efficient formulation and precise application of those corrective actions. Corrective actions can include absolute, adaptive, or replacement-type modifications to the detected layout imperfections. A concurrent processing methodology can be used to minimize processing overhead during layout beautification, and the actions can also be incorporated into a lookup table to further reduce runtime. A layout beautification system can also be connected to a network across which shapes, actions, and IC layout data files can be accessed and retrieved.

Shape-Based Geometry Engine To Perform Smoothing And Other Layout Beautification Operations

Disclosed is a method of setting a process parameter for use in manufacturing a semiconductor integrated circuit, comprising correcting a first pattern by using process parameter information to obtain a second pattern, the first pattern being one which corresponds to a design layout of the semiconductor integrated circuit, predicting a third pattern by using the process parameter information, the third pattern being one which corresponds to the second pattern and which is to be formed on a semiconductor wafer in an etching process, obtaining an evaluation value by comparing the third pattern with the first pattern, determining whether the evaluation value satisfies a preset condition, and changing the process parameter information when the evaluation value is found not to satisfy the preset condition.

Method of setting process parameter and method of setting process parameter and/or design rule

First and second virtual grates are defined as respective sets of parallel virtual lines extending across a layout area in first and second perpendicular directions, respectively. The virtual lines of the first and second virtual grates correspond to placement locations for layout features in lower and higher chip levels, respectively. Each intersection point between virtual lines of the first and second virtual grates is a gridpoint within a vertical connection placement grid. Vertical connection structures are placed at a number of gridpoints within the vertical connection placement grid so as to provide electrical connectivity between layout features in the lower and higher chip levels. The vertical connection structures are placed so as to minimize a number of different spacing sizes between neighboring vertical connection structures across the vertical connection placement grid, while simultaneously minimizing to an extent possible layout area size. The vertical connection structures may be contacts or vias.

Methods for defining contact grid in dynamic array architecture

A cell circuit and corresponding layout is disclosed to include linear-shaped diffusion fins defined to extend over a substrate in a first direction so as to extend parallel to each other. Each of the linear-shaped diffusion fins is defined to project upward from the substrate along their extent in the first direction. A number of gate level structures are defined to extend in a conformal manner over some of the number of linear-shaped diffusion fins. Portions of each gate level structure that extend over any of the linear-shaped diffusion fins extend in a second direction that is substantially perpendicular to the first direction. Portions of each gate level structure that extend over any of the linear-shaped diffusion fins form gate electrodes of a corresponding transistor. The diffusion fins and gate level structures can be placed in accordance with a diffusion fin virtual grate and a gate level virtual grate, respectively.

Cell circuit and layout with linear finfet structures

A rectangular interlevel connector array (RICA) is defined in a semiconductor chip. To define the RICA, a virtual grid for interlevel connector placement is defined to include a first set of parallel virtual lines that extend across the layout in a first direction, and a second set of parallel virtual lines that extend across the layout in a second direction perpendicular to the first direction. A first plurality of interlevel connector structures are placed at respective gridpoints in the virtual grid to form a first RICA. The first plurality of interlevel connector structures of the first RICA are placed to collaboratively connect a first conductor channel in a first chip level with a second conductor channel in a second chip level. A second RICA can be interleaved with the first RICA to collaboratively connect third and fourth conductor channels that are respectively interleaved with the first and second conductor channels.

Methods for multi-wire routing and apparatus implementing same

A method and apparatus for providing correction for microloading effects is described. Hybrid proximity correction techniques are used to make the problem computationally more feasible. More specifically, feature edges in a layout can be grouped into those edges, or edge segments, with a large edge separation (group B), e.g. greater than n, and those having less than that separation (group A). The group B features can then be corrected for microloading effects rapidly using rules based correction. Then both groups of edges can be corrected using model based optical proximity correction using the output of the rule based correction as the ideal, or reference, layout.

Hua-yu Liu

Papers

Microloading effect correction