From the Publisher:
A complete guide to testing, analyzing, verifying, and monitoring real-time systems
More and more of our modern-day systems and devices-from toasters and climate-control systems to airplanes and space shuttles-contain embedded systems to control their functions and ensure that their responses are both timely and correct. With safety a requisite factor, performance validation is a critical aspect of real-time systems. Answering the needs of professionals and students alike, Real-Time Systems: Scheduling, Analysis, and Verification provides a substantial, up-to-date overview of the verification and validation process. It describes several approaches to the problem, and examines the advantages and disadvantages of each approach.
Designed to be both an introductory text and a handy reference for the practitioner, the book discusses:
Symbolic logic, automata, and languages in non-real-time systems
Real-time scheduling and schedulability analysis
Verification using timed automata and timed petri nets
Process algebra
The design and analysis of propositional-logic rule-based systems
Timing analysis of predicate-logic rule-based systems
Optimization of rule-based systems
Model checking, real-time logic, and statecharts


With ample illustrations and examples of a variety of industrial and toy applications, Real-Time Systems: Scheduling, Analysis, and Verification serves as a key resource for every professional who works with real-time systems.

Real-Time Systems: Scheduling, Analysis, and Verification

RuleBase is a formal verification tool, developed by the IBM Haifa Research Laboratory. It is the result of three years of experience in practical formal verification of hardware which, we believe, has been a key factor in bringing the tool to its current level of maturity. We present the tool, including several unique features, and summarize our usage experience.

/pdf/rulebase-an-industry-oriented-formal-verification-tool-5emuvyln1s.pdf

RuleBase: an industry-oriented formal verification tool

A programmed computer generates descriptions of circuits (called “checkers”) that flag functional defects in a description of a circuit undergoing functional verification. The programmed computer automatically converts the circuit's description into a graph, automatically examines the graph for instances of a predetermined arrangement of nodes and connections, and automatically generates instructions that flag a behavior of a device represented by the instance in conformance with a known defective behavior. The checkers can be used during simulation or emulation of the circuit, or during operation of the circuit in a semiconductor die. The circuit's description can be in Verilog or VHDL and the automatically generated checkers can also be described in Verilog or VHDL. Therefore, the checkers can co-simulate with the circuit, monitoring the simulated operation of the circuit and flagging defective behavior. The programmed computer can automatically determine load conditions of registers in the circuit and automatically generate checkers to flag data loss in the registers. Some of the checkers may use signals generated by other checkers.

Method for automatically generating checkers for finding functional defects in a description of a circuit

We present a design and verification methodology for hybrid dynamical systems. Our approach is based on optimal control and game theory. The hybrid design is seen as a game between two players. One is the disturbances that enter the dynamics. The disturbances can encode the actions of other agents (in a multi-agent setting), the actions of high level controllers or unmodeled environmental disturbances. The second player is the control, which is to be chosen by the designer. The two players compete over cost functions that encode the properties that the closed loop hybrid system needs to satisfy (e.g. safety). The control “wins” the game if it can keep the system “safe” for any allowable disturbance. The solution to the game theory problem provides the designer with continuous controllers as well as sets of safe states where the control “wins” the game. These safe sets can be used to construct an interface that guarantees the safe operation of the combined hybrid system. Extensions of this approach can also be used for verification of hybrid systems as well as the generation of abstractions of the lower layer behavior (e.g. timed abstractions).

A game-theoretic approach to hybrid system design

This dissertation presents a hierarchical, hybrid point of view to the control of large-scale systems. The analysis is based on a new hybrid dynamical system formulation that allows for the modelling of large scale systems in a modular fashion. Three problems are addressed: controller design, closed loop performance verification and the extension of system autonomy. A control scheme based on semi-autonomous agent operation is first proposed. An algorithm, using ideas from game theory, is presented to produce continuous controllers for hierarchical, hybrid designs. A discussion of design issues involving controller autonomy is presented. The emphasis is on hybrid effects. The hierarchical and hybrid issues involved in the design of a fault tolerant control scheme are investigated. The study concludes with a case study on the application of the proposed techniques to the control of an automated highway system (AHS).

/pdf/hierarchical-hybrid-control-of-large-scale-systems-2bmngr4o5f.pdf

Hierarchical, Hybrid Control of Large Scale Systems

Functional and timing verification are currently the bottlenecks in many design efforts. Simulation and emulation are extensively used for verification. Formal verification is now gaining acceptance in advanced design groups. This has been facilitated by the use of binary decision diagrams (BDDs). This paper describes the essential features of HSIS, a BDD-based environment for formal verification: 1. Open language design, made possible by using a compact and expressive intermediate format known as BLIF-MV. Currently, a synthesis subset of Verilog is supported. 2. Support for both model checking and language containment in a single unified environment, using expressivefairness constraints. 3. Efficient BDD-based algorithms. 4. Debugging environment for both language containment and model checking. 5. Automatic algorithms for the early quantification problem. 6. Support for state minimization using bisimulation and similar techniques. HSIS allows us to experiment with formal verification techniques on a variety of design problems. It also provides an environment for further research in formal verification.

/pdf/hsis-a-bdd-based-environment-for-formal-verification-3jhlq31ofz.pdf

HSIS: A BDD-Based Environment for Formal Verification

We present an approach to compute all input don't care sequences for a component in an FSM network with an arbitrary topology. In a cascade FSM network, Kim and Newborn's (K-N) procedure exactly computes all input don't care sequences for the driven machine. However, for a component in a general FSM network the problem of computing and exploiting input don't care sequences is unsolved. We demonstrate that this problem can be reduced to one for a cascade circuit. This reduction uses the notion of an abstract driving machine. In some cases, the exact computation and exploitation of these sequences may be too expensive. We propose methods to compute subsets of input don't care sequences. We discuss the implementation of these algorithms using implicit methods. We also present approximate methods for managing the complexity of large FSM networks. Finally, we give some preliminary results on small networks.

Input don't care sequences in FSM networks

Previous attempts to capture the phenomenon of output don't care sequences for a component in an FSM network have been incomplete. We demonstrate that output don't care sequences for a component can be expressed using a set of observability relations given that its state transition function is kept unchanged. Each observability relation is permissible in the sense that any implementation compatible with one of them is feasible. The representation for a set of permissible observability relations is not unique. We provide a method to find a set with the minimum number of permissible relations. We briefly discuss the exploitation of permissible observability relations in state minimization, circuit implementation and signal encoding. We have implemented these methods and present some preliminary results on a few small artificially constructed examples.

/pdf/permissible-observability-relations-in-fsm-networks-15hpzqper3.pdf

Permissible Observability Relations in FSM Networks

Current approaches to compute and exploit the flexibility of a component in an FSM network are all at the symbolic level. Conventionally, exploitation of this flexibility relies on state minimizers for incompletely specified FSMs (ISFSMs) or pseudo non-deterministic FSMs (PNDFSM's). However, state-of-the art state minimizers cannot handle large ISFSMs or PNDFSMs. In addition, these exploitation techniques are at the symbolic level, not directly at the net-list logic level. We present a general approach to exploit exact or approximate flexibility directly at the net-list logic level, and we demonstrate that many sequential logic optimization techniques can be applied in exploitation. Moreover, we propose a new procedure for input don't care sequences. As a result, both computation and exploitation of input don't care sequences in larger FSM networks can be made efficient and effective. Finally, we give preliminary results on some artificially constructed FSM networks. Preliminary results indicate that our approach can be effective in reducing the size of a component of an FSM network.

/pdf/multi-level-logic-optimization-of-fsm-networks-33o3v6s7ta.pdf

Huey-Yih Wang

Papers

HSIS: A BDD-Based Environment for Formal Verification

Input don't care sequences in FSM networks

Permissible Observability Relations in FSM Networks

Multi-level logic optimization of FSM networks