This work presents a phase-locked loop for clock generation that consists of a phase/frequency detector, charge pump, loop filter, range-programmable voltage-controlled ring oscillator, and programmable divider. The phase/frequency detector and charge pump are designed to reduce the dead zone and charge sharing for enhancing the locking performance, respectively. In the design of the range-programmable voltage-controlled oscillator, the original inverter ring of a delay line is divided into several smaller ones, and then they are recombined in parallel to each other. Programming the number of paralleled inverter rings allows us to generate the wide-range clock frequencies. This design shuts off some inverters that are not in use to reduce power consumption. To allow the phase-locked loop to shut off inverters, the feasibility of using controllable inverters by the output-switch and power-switch schemes is explored. Theoretical analyses indicate that power consumption of the voltage-controlled oscillator depends on transistors' sizes rather than operating frequencies. By applying the TSMC 0.35-/spl mu/m CMOS technology, the proposed phase-locked loop that uses the power-switch scheme can yield clock signals ranging from 103 MHz to 1.02 GHz at a supply voltage of 1.8 V. Moreover, power dissipation that is proportional to the number of paralleled inverter rings is measured with 1.32 to 4.59 mW. The phase-locked loop proposed herein can be used in various digital systems, providing power-efficient and wide-range clock signals for task-oriented computations.

A power-efficient wide-range phase-locked loop

In this paper, a voltage-controlled ring oscillator (VCO) with wide linear tuning frequency range capability, based on transmission gates, is described. It also features a rapid voltage swing and a 50% duty cycle independent of the control voltage. Fabricated in the TSMC 0.35 /spl mu/m 1P4M, 3.3 V CMOS process, the VCO achieves an operating frequency range of 4.8 Hz to 256 MHz. The measured peak-to-peak and rms jitter are 41 ps and 5.8 ps while operating at 200 MHz.

Wide frequency range voltage controlled ring oscillators based on transmission gates

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Oscillation Control in CMOS Phase-Locked Loops

A voltage-controlled ring oscillator based on an FGMOS transistor

This paper describes a dual-looped PLL architecture to improve voltage-to-frequency linearity of the VCO. The designed VCO operates at a wide frequency range of 75.8 MHz-1 GHz with a good linearity. A PFD circuit preventing fluctuation of the charge pump circuit under the locked condition is designed. Experimental results show that the phase noise of the VCO with a V-I converter is -100.3 dBc/Hz at a 100 kHz offset frequency and the power dissipation is 92 mW.

A 3.3 V high speed CMOS PLL with 3-250 MHz input locking range

A 3.3 V PLL (Phase Locked Loop) is designed for a high frequency, low voltage, and low power applications. This paper proposes a new PLL architecture to improve voltage-to frequency linearity of VCO (Voltage Controlled Oscillator). The designed VCO operates at a wide frequency range of 75.8 MHz-1 GHz with a good linearity. PFD (Phase Frequency Detector) circuit preventing fluctuation of the charge pump circuit under the locked condition is presented. The simulation results of the PLL with a standard 0.6 /spl mu/m CMOS technology illustrate a locking time of 3.5 /spl mu/s/spl plusmn/100 ps jitter and a power dissipation of 92 mW at 1 GHz operating frequency with 125 MHz of input frequency.

Hyuk-Jun Sung

Papers

A 3.3 V high speed CMOS PLL with 3-250 MHz input locking range

A 3.3 V high speed dual looped CMOS PLL with wide input locking range