An amplifier with integrated filter (e.g., an LNA) is described. In one design, the amplifier may include a gain stage, a filter stage, and a buffer stage. The gain stage may provide signal amplification for an input signal. The filter stage may provide filtering for the input signal. The buffer stage may buffer a filtered signal from the filter stage. The amplifier may further include a second filter stage and a second buffer stage. The second filter stage may provide additional filtering for the input signal. The second buffer stage may buffer a second filtered signal from the second filter stage. All of the stages may be stacked and coupled between a supply voltage and circuit ground. The filter stage(s) may implement an elliptical lowpass filter. Each filter stage may include an inductor and a capacitor coupled in parallel and forming a resonator tank to attenuate interfering signals.

Amplifier with integrated filter

A current-reused quadrature voltage-controlled oscillator (CR-QVCO) is proposed with the cross-coupled transformer-feedback technology for the quadrature signal generation. This CR-QVCO has the advantages of low-voltage/low-power operation with an adequate phase noise performance. A compact differential three-port transformer, in which two half-circle secondary coils are carefully designed to optimize the effective turn ratio and the coupling factor, is newly constructed to satisfy the need of signal coupling and to save the area consumption simultaneously. The quadrature oscillator providing a center frequency of 7.128 GHz for the ultrawideband (UWB) frequency synthesizer use is demonstrated in a 0.18 mum RF CMOS technology. The oscillator core dissipates 2.2 mW from a 1 V supply and occupies an area of 0.48 mm2. A tuning range of 330 MHz (with a maximum control voltage of 1.8 V) can be achieved to stand the frequency shift caused by the process variation. The measured phase noise is -111.2 dBc/Hz at 1 MHz offset from the center frequency. The IQ phase error shown is less than 2deg. The calculated figure-of-merit (FOM) is 184.8 dB.

A 1 V 2.2 mW 7 GHz CMOS Quadrature VCO Using Current-Reuse and Cross-Coupled Transformer-Feedback Technology

A Ku-band CMOS voltage-controlled oscillator (VCO) constructed in a modified current-reused configuration is presented in this letter. Two dc level shifters combined into two metal-insulator-metal capacitors are adopted to solve the transconductance and load mismatch problems of the conventional current-reused VCO for obtaining more symmetrical oscillation signals and lowering the phase noise of oscillator. A prototype was designed and measured to verify the design concept. The measurement results demonstrate the central oscillation signal of 16 GHz to be associated with the 900 MHz tuning range and -111 dBc/Hz phase noise at 1 MHz offset. The power consumption of the VCO core is only 8.1 mW. The measurement result evaluated by means of a figure of merit is about -186.8 dBc/Hz.

Low Phase-Noise and Low-Power CMOS VCO Constructed in Current-Reused Configuration

This letter presents a backgate coupled quadrature voltage-controlled oscillator (QVCO) which consists of a pair of current reused LC-VCOs. The proposed QVCO is designed for 2-GHz operation based on a 0.18-mum triple-well CMOS technology. Measurements show -102 and -124dBc/Hz at 100-kHz and 1-MHz offset, respectively. Compared to the conventional QVCO, the proposed QVCO dissipates significantly lower power (1.74mA from a 1.25-V supply) while showing good 1/f3 close-in phase noise

A 2.2-mW Backgate Coupled $LC$ Quadrature VCO With Current Reused Structure

A low power and high linearity UWB low noise amplifier (LNA) for 3.1-10.6GHz wireless applications in 0.13µm CMOS process

An LC-VCO with halt of the power dissipation of a that of the conventional topology is presented. The LC-VCO replaces one of the NMOSFET of the conventional differential LC-VCO with a PMOSFET. The operational principles and design guidelines of the proposed topology are reported. The proposed LC-VCO is implemented in a 0.18 /spl mu/m CMOS technology for 2GHz applications and measurements show phase noise is -103dBc/Hz at 100kHz offset while dissipating 1mW from a 1.25V supply.

A 1mW current-reuse CMOS differential LC-VCO with low phase noise

In this paper, a set up noise parameter expression and the third order intermodulation product expression (IM3) for a power-constrained simultaneous noise and input matching low noise amplifier design optimization technique are introduced. Based on these expressions, the methodology to design LNA to archive the power-constrained simultaneous noise and input matching as well as satisfy the linearization condition is explained. In additional, the power gain is enhanced by using a very simple positive feedback. The proposed LNA for 5 GHz WLAN applications is fabricated based on 0.18 /spl mu/m CMOS technology. Measured results show 20 dB power gain, 1.5 dB NF and -5 dBm IIP3. The proposed LNA dissipates DC current of 3 mA at supply voltage of 2.5 V.

CMOS low noise amplifier design optimization technique

This paper represents a low noise, high gain image rejection low noise amplifier (IR-LNA) used in the superheterodyne architecture. The proposed IR-LNA is implemented by integrating the low noise, high gain LNA with the proposed third order active notch filter, which is optimized for 5.25 GHz WLAN with IF frequency of 500 MHz applications. The measurement results show power gain of 20.5 dB, lower than 1.5 dB NF, and image rejection of 26 dB. Two-tone test results indicate -5 dBm and -8 dBm of IIP3 for the case of using and not using the notch filter, respectively. The proposed IR-LNA operates at supply voltage of 3 V, and dissipates 4 mA in 0.18 /spl mu/m CMOS technology.

Hyung-Chul Choi

Papers

A 1mW current-reuse CMOS differential LC-VCO with low phase noise

CMOS low noise amplifier design optimization technique

A 5.2 GHz image rejection CMOS low noise amplifier for WLAN applications