This paper presents a mostly digital multiplying delay-locked loop (MDLL) architecture that leverages a new time-to-digital converter (TDC) and a correlated double-sampling technique to achieve subpicosecond jitter performance. The key benefit of the proposed structure is that it provides a highly digital technique to reduce deterministic jitter in the MDLL output with low sensitivity to mismatch and offset in the associated tuning circuits. The TDC structure, which is based on a gated ring oscillator (GRO), is expected to benefit other PLL/DLL applications as well due to the fact that it scrambles and first-order noise shapes its associated quantization noise. Measured results are presented of a custom MDLL prototype that multiplies a 50 MHz reference frequency to 1.6 GHz with 928 fs rms jitter performance. The prototype consists of two 0.13 μm integrated circuits, which have a combined active area of 0.06 mm 2 and a combined core power of 5.1 mW, in addition to an FPGA board, a discrete DAC, and a simple RC filter.

A Highly Digital MDLL-Based Clock Multiplier That Leverages a Self-Scrambling Time-to-Digital Converter to Achieve Subpicosecond Jitter Performance

Ring oscillator (RO)-based clock multipliers are traditionally used for clocking digital systems such as processors. While they are most commonly implemented using PLLs, it is becoming increasingly difficult to design them in a power efficient manner, as their jitter requirements grow more stringent. Recognizing that the main limitation of PLLs arises from limited RO noise suppression bandwidth (NBW = F REF /10), multiplying delay-locked loops (MDLLs) that suppress noise by replacing a RO's noisy edge with a clean reference clock edge have gained prominence [1–3]. Such an edge replacement operation suppresses RO noise with an increased NBW of about F REF /4 [1]. However, imperfections of edge replacement logic have limited the output frequency of MDLLs [1, 2] or degraded their jitter performance at frequencies beyond 2.5GHz [3]. Furthermore, MDLLs are susceptible to transistor non-idealities and require elaborate analog calibration schemes that are prone to circuit imperfections [2, 3]. In contrast to PLLs and MDLLs, injection-locked clock multipliers (ILCMs) lock RO frequency to an integer multiple (N) of F REF by injecting narrow pulses at F REF into the RO whose free running frequency is about NF REF [4]. Because ILCMs do not require logic that needs to adhere to stringent timing requirements (like MDLLs) they are better suited for generating high frequencies. However, their jitter performance is limited by: (i) smaller NBW (≈ F REF /6) compared to MDLLs, (ii) limited suppression of RO flicker noise due to their Type-I response, and (iii) the need for RO free running frequency, F FR , to be close to NF REF for maintaining low jitter performance across voltage and temperature. These factors limit the multiplication factor (usually to less than 10) and degrade power efficiency [4,5]. In this paper, we present an ILCM architecture that achieves a NBW of close to F REF /3 with a jitter of 335fs rms at 5GHz, while operating with F REF = 125MHz and consuming 5.3mW.

8.6 A 2.5-to-5.75GHz 5mW 0.3ps rms -jitter cascaded ring-based digital injection-locked clock multiplier in 65nm CMOS

In this paper, we propose a low-jitter low-power digital multiplying delay-locked loop (MDLL) with a self-calibrated double reference injection scheme. To reduce jitter, the noisy edge of the oscillator is replaced by both the rising and falling edges of the clean reference, which results in 6-dB reduction in phase noise compared with a conventional single-edge injection MDLL. Reference spur caused by a frequency error of the oscillator, duty-cycle error of the reference, and circuit imperfection, such as offset and mismatch, is removed by employing three background feedback loops with a shared analog pulsewidth comparator. Implemented in 28-nm CMOS, the proposed digital MDLL generates 2.4-GHz clock and achieves a spur of −51.4 dBc and an rms jitter of 699 ${\mathrm{ fs}}_{\mathrm{ rms}}$ while consuming 1.5 mW from 1-V supply.

A 2.4-GHz 1.5-mW Digital Multiplying Delay-Locked Loop Using Pulsewidth Comparator and Double Injection Technique

A low-jitter and low-reference-spur ring-type voltage-controlled oscillator (VCO)-based switched-loop filter (SLF) phase-locked loop (PLL) is presented. To enhance the capability of suppressing jitter of a VCO, we propose a fast phase-error correction (FPEC) technique that emulates the phase-realignment mechanism of an injection-locked clock multiplier. By the proposed FPEC technique, accumulated jitter of a VCO can be removed intensively in a short interval, thereby suppressing jitter dramatically. Based on a PLL topology having an intrinsic integrator in a VCO, the proposed architecture can also achieve a low reference spur despite a high multiplication factor (i.e., 64). This paper also presents the selective frequency-tuning technique used in the VCO that helps the proposed architecture further suppress the level of reference spur. The proposed PLL was fabricated in a 65-nm CMOS process. The measured rms jitter integrated from 1 kHz to 80 MHz and the reference spur of the output signal with a 3.008-GHz frequency were 357 fs and −71 dBc, respectively. The total active area was 0.047 mm2, and the power consumption was 4.6 mW.

A Low-Jitter and Low-Reference-Spur Ring-VCO-Based Switched-Loop Filter PLL Using a Fast Phase-Error Correction Technique

Ring-oscillator (RO)-based phase-locked loops (PLLs) are very attractive for system-on-chip applications for their compactness and tuning range, but suffer from high jitter and supply noise sensitivity. This paper presents a sub-sampling phase detector (SSPD)-based feedforward noise cancellation (FFNC) technique to improve these drawbacks of the RO PLL. The FFNC scheme utilizes the already available SSPD output to perform cancellation with high sensitivity while utilizing low power and area overhead. The 2- to 2.8-GHz RO PLL proof-of-principle prototype occupies 0.022 mm2 active area in 65 nm CMOS; it achieves a 633 fs rms jitter at 2.36 GHz with 5.86 mW power consumption and an figure of merit (FOMjitter) of −236.3 dB. The cancellation reduces the jitter by $1.4\times $ , the phase noise by 10.2 dB to −123.5 dBc/Hz at 300-kHz offset, and the RO supply sensitivity by 19.5 dB for a 1 mVpp 100-kHz noise tone on the RO supply.

A Low-Jitter Ring-Oscillator Phase-Locked Loop Using Feedforward Noise Cancellation With a Sub-Sampling Phase Detector

A multiplying delay-locked loop (MDLL) is an attractive architecture for a low-jitter clock generator, as it does not suffer much from jitter accumulation [1–4]. By periodically replacing the output edge of the oscillator by a clean edge of the reference, an MDLL has a large effective loop bandwidth for oscillator phase noise, which cannot be obtained in a PLL. With this advantage in mind, several MDLLs have been implemented recently [2], [3]. Unfortunately, these works are limited in their practical use as the frequency multiplication factor is only 4 [2] or 8 [3]. While the prior works show good jitter performance, it is primarily due to their wide effective loop bandwidth of nearly one hundred MHz that arises from using reference frequencies of 375 to 575MHz. It is much more challenging to achieve same level of jitter performance if the multiplication factor is increased and reference frequency is decreased. In this work, a low-power digital MDLL (DMDLL) with a multiplication factor of 32 is presented. To achieve low-jitter despite the large multiplication factor, a background-calibrated double-injection scheme is proposed which exploits both the rising and falling edge of the reference.

19.3 A 2.4GHz 1.5mW digital MDLL using pulse-width comparator and double injection technique in 28nm CMOS

Since the advent of digital PLLs (DPLLs), various techniques have been proposed fora low-power, low-noise fractional-N frequency synthesizer. Among the various innovations, a reference-multiplied architecture offers distinct advantages compared to conventional DPLLs [1]. First, low quantization noise (q-noise) can be achieved without complex q-noise cancellation schemes, since the delta-sigma modulator (DSM) has a high oversampling ratio and its q-noise is pushed to higher frequencies. Second, noise requirements of PLL building blocks become less stringent as the division value is reduced. For a digital PLL using a Nyquist-rate time-to-digital converter (TDC), if the reference is multiplied by N the time resolution of the TDC can be reduced by √N for the same noise level. Unfortunately, one drawback of the reference-multiplied PLL is the increase in power and complexity due to the reference-multiplying circuit. In this paper, we propose a reference-multiplied digital fractional-N PLL that has negligible overhead in the reference-multiplying circuit. To save power, a frequency-multiplied TDC (FMTDC) consisting of an open-loop multiplying DLL (MDLL) and a Vernier delay-line (VDL) TDC is proposed, which share their delay lines. High spurious tone coming from the open-loop MDLL is canceled by an adaptive filter located between TDC and loop filter.

14.4 A 5GHz −95dBc-reference-Spur 9.5mW digital fractional-N PLL using reference-multiplied time-to-digital converter and reference-spur cancellation in 65nm CMOS

Hyunik Kim

Papers

19.3 A 2.4GHz 1.5mW digital MDLL using pulse-width comparator and double injection technique in 28nm CMOS

14.4 A 5GHz −95dBc-reference-Spur 9.5mW digital fractional-N PLL using reference-multiplied time-to-digital converter and reference-spur cancellation in 65nm CMOS

Field emission and x-ray effect on RAON half-wave resonator (HWR) superconducting cavity performance