algorithmics and modular computations, Theory of Codes and Cryptography (3).From an analytical 1. RE Blahut. Theory and practice of error control codes. eecs.uottawa.ca/∼yongacog/courses/coding/ (3) R.E. Blahut,Theory and Practice of Error Control Codes, Addison Wesley, 1983. QA 268. Cached. Download as a PDF 457, Theory and Practice of Error Control CodesBlahut 1984 (Show Context). Citation Context..ontinued fractions.

Theory and practice of error control codes

We are experiencing an explosive growth in the number of consumer devices, including smartphones, tablets, web-based computers such as Chromebooks, and wearable devices. For this class of devices, energy efficiency is a first-class concern due to the limited battery capacity and thermal power budget. We find that data movement is a major contributor to the total system energy and execution time in consumer devices. The energy and performance costs of moving data between the memory system and the compute units are significantly higher than the costs of computation. As a result, addressing data movement is crucial for consumer devices. In this work, we comprehensively analyze the energy and performance impact of data movement for several widely-used Google consumer workloads: (1) the Chrome web browser; (2) TensorFlow Mobile, Google's machine learning framework; (3) video playback, and (4) video capture, both of which are used in many video services such as YouTube and Google Hangouts. We find that processing-in-memory (PIM) can significantly reduce data movement for all of these workloads, by performing part of the computation close to memory. Each workload contains simple primitives and functions that contribute to a significant amount of the overall data movement. We investigate whether these primitives and functions are feasible to implement using PIM, given the limited area and power constraints of consumer devices. Our analysis shows that offloading these primitives to PIM logic, consisting of either simple cores or specialized accelerators, eliminates a large amount of data movement, and significantly reduces total system energy (by an average of 55.4% across the workloads) and execution time (by an average of 54.2%).

Google Workloads for Consumer Devices: Mitigating Data Movement Bottlenecks

Provided are a memory system and an operating method thereof. The operating method reads an observation memory cell at least one time with different read voltages to configure a first read data symbol, reads a plurality of interference memory cells adjacent to the observation memory cell at least one time with different read voltages to configure second read data symbols, and determines a logical value of the observation memory cell based on the first read data symbol and the second read data symbols.

Memory system and operating method thereof

This paper presents a high-performance general-purpose no-reference (NR) image quality assessment (IQA) method based on image entropy. The image features are extracted from two domains. In the spatial domain, the mutual information between different color channels and the two-dimensional entropy are calculated. In the frequency domain, the statistical characteristics of the two-dimensional entropy and the mutual information of the filtered subband images are computed as the feature set of the input color image. Then, with all the extracted features, the support vector classifier (SVC) for distortion classification and support vector regression (SVR) are utilized for the quality prediction, to obtain the final quality assessment score. The proposed method, which we call entropy-based no-reference image quality assessment (ENIQA), can assess the quality of different categories of distorted images, and has a low complexity. The proposed ENIQA method was assessed on the LIVE and TID2013 databases and showed a superior performance. The experimental results confirmed that the proposed ENIQA method has a high consistency of objective and subjective assessment on color images, which indicates the good overall performance and generalization ability of ENIQA. The implementation is available on github https://github.com/jacob6/ENIQA
 .

/pdf/no-reference-color-image-quality-assessment-from-entropy-to-565xd2jngs.pdf

No-reference color image quality assessment: from entropy to perceptual quality

Methods, systems, and computer readable media for providing a flexible host memory buffer are disclosed. One method includes allocating an amount of host memory as a host memory buffer accessible by a solid state drive (SSD) as a cache for SSD data. The method further includes caching data from the solid state drive in the host memory buffer. The method further includes monitoring utilization of the host memory buffer. The method further includes dynamically increasing or decreasing the amount of host memory allocated for the host memory buffer based on the utilization.

Methods, systems, and computer readable media for providing flexible host memory buffer

Aspects include systems and methods for increasing performance of a flash translation layer (FTL) of a flash memory device. A copy of FTL tables stored on a flash memory device may be copied to a memory of a host device. The copy of the FTL tables may be directly accessed by the flash memory device to translate between logical addresses provided by the host device for read/write operations from/to a flash memory of the flash memory device, and the respective physical addresses of the flash memory. The flash memory device is granted direct memory access to a portion of the memory of the host device where the copy of the FTL tables is stored. The flash memory device bus masters communication busses connecting the flash memory device to the memory of the host device.

System and method for high performance and low cost flash translation layer

Systems and methods are disclosed for providing logical-to-physical address translation for a managed NAND flash storage device. One embodiment is a system comprising a system on chip (SoC) electrically coupled to a volatile memory device. A direct memory access (DMA) controller is electrically coupled to the SoC. The DMA controller receives a logical address to be translated to a physical address associated with a managed NAND flash storage device. A cache controller is configured to fetch from the volatile memory device a portion of a logical-to-physical (L2P) address table comprising a compressed version of a L2P mapping for the logical address. A compression block is configured to decompress the compressed version of the L2P mapping to determine the physical address corresponding to the logical address.

Compressed caching of a logical-to-physical address table for nand-type flash memory

Motivated by the significant storage footprint of OS/Apps in mobile devices, this paper studies the realization of OS/Apps transparent compression. In spite of its obvious advantage, this feature however is not widely available in commercial mobile devices, which is due to the justifiable concern on the read latency penalty. In conventional practice on implementing transparent compression, read latency overhead comes from two aspects, including read amplification and decompression computational latency. This paper presents simple yet effective design solutions to eliminate the read amplification at the filesystem level and eliminate the computational latency overhead at the computer architecture level. To demonstrate its practical feasibility, we first implemented a prototyping filesystem to empirically verify the realization of transparent compression with zero read amplification. We further demonstrated that the OS/Apps footprint can be reduced by up to 39 percent on a Nexus 7 tablet installed with Android 5.0. Through application-specific integrated circuit (ASIC) synthesis, we show that the proposed computer architecture level design solution can eliminate the decompression latency overhead with very small silicon cost.

Realizing Transparent OS/Apps Compression in Mobile Devices at Zero Latency Overhead

A system for replacing a page stored in system memory when reading the page incurs a multiple-bit error. Upon reading a page in system memory for which a multiple-bit error is detected, backup data in flash memory is loaded into a redundant page in the system memory, and a re-mapper is configured so that future accesses to the page are redirected to the redundant page.

Method and apparatus for multiple-bit dram error recovery

Removable memory card type detection systems and methods are disclosed. In one aspect, a removable memory card is inserted into a receptacle of a host. The host determines a type of removable memory card based upon either electrical or physical properties of the removable memory card. In this manner, if the host detects that the removable memory card possesses certain electrical or physical properties associated with a microSD card, the host determines that the removable memory card is a microSD type card. If the host detects that the removable memory card possesses certain electrical or physical properties associated with a UFS card, the host determines that the removable memory card is a UFS type card. By determining the card type based on detection of certain electrical or physical properties, aspects disclosed herein are able to distinguish between UFS and microSD cards without requiring an additional pin or card initialization time.

Hyunsuk Shin

Papers

System and method for high performance and low cost flash translation layer

Compressed caching of a logical-to-physical address table for nand-type flash memory

Realizing Transparent OS/Apps Compression in Mobile Devices at Zero Latency Overhead

Method and apparatus for multiple-bit dram error recovery

Removable memory card type detection systems and methods