Multi-functional systolic array with reconfigurable micro-power processing elements

Address generators for linear systolic array

This paper gives design of “Evolutionary program based synthesis of systolic architecture for 3-Tap FIR filter, 2*2 Matrix-Matrix multiplication, convolution and correlation of two discrete sequences”. Results indicate that evolutionary approach is the best search method that can be adopted on systolic architectures as it was inferred from literature survey. In most general terms, evolution can be described as a two–step iterative process, consisting of random variation followed by selection. In this project strategy of Gaussian perturbation having ten competitions, thousand trails and varying populations is choosen as the designs are relatively simple. For this each design is represented in Dependency Graph (DG) from design algorithm (for example FIR equation). This DG is further transformed to Space –Time representation after the application of linear mapping technique. The transformation is done based on three vectors viz., Projection Vector, Processor Vector and scheduling Vector. The design concept is at system level; hence the terminology used in the project to some extent requires knowledge of advances in computer architecture and also knowledge of multiple disciplines. Only four typical designs are considered; further it can be extended to other design as well in specific to DSP designs. Each MATLAB program written is verified manually for all possible test cases. Results are reported with errors encountered. In future it is expected that evolutionary based concepts are the real contributors for next generation architecture level design.

/pdf/evolutionary-program-based-synthesis-of-systolic-array-4eblgigei0.pdf

Evolutionary Program Based Synthesis of Systolic Array

Design of a Power Aware Systolic Array based Support Vector Machine Classifier

In recent times, there is an increasing interest in compressed-domain image analysis and its VLSI implementation due to extensive use multimedia communication, specially in mobile devices. This paper deals with the semi systolic architecture of DCT-based (discrete cosine transform) image resizing processor as a compressed domain image processing element. Further, we propose an efficient method for VLSI implementation for DCT-domain image resizing transformation with bidirectional linear semi-systolic array. This method is developed from the investigation of the DCT-domain image resizing operation through a parallel processing of the matrix operations. The use of systolic arrays as a processing block of the matrix operations reduces the number of computation and also amenable for VLSI implementation.

A bidirectional linear semi-systolic architecture for DCT-domain image resizing processor

This paper addresses the problem of rectangular matrix multiplication on bidirectional linear systolic arrays (SAs). We analyze all bidirectional linear SAs in terms of efficiency. We conclude that the efficiency depends on the relation between the loop boundaries in the systolic algorithm (i.e. matrix dimensions). We point out which SA is the best choice depending on the relation between matrix dimensions. We have designed bidirectional linear systolic arrays suitable for rectangular matrix multiplication.

/pdf/matrix-multiplication-on-bidirectional-linear-systolic-4ibyh8yghn.pdf

I Emina Milovanovic

Papers

Matrix multiplication on bidirectional linear systolic arrays