It is shown that clock frequencies in excess of 200 MHz are feasible in a 3- mu m CMOS process. This performance can be obtained by means of clocking strategy, device sizing, and logic style selection. A precharge technique with a true single-phase clock, which increases the clock frequency and reduces the skew problems, is used. Device sizing with the help of an optimizing program improves circuit speed by a factor of 1.5-1.8. The logic depth is minimized to one instead of two or more, and pipeline structures are used wherever possible. Experimental results for several circuits which work at clock frequencies of 200-230 MHz are presented. SPICE simulation shows that some circuits could work up to 400-500 MHz. >

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High-speed CMOS circuit technique

Two of the main consequences of advances in VLSI technologies are increased cost of design and wiring. In CMOS synchronous systems, this cost is partly due to tedious synchronization of different clock phases and routing of these clock signals. Here, a single-phase clocking scheme that makes the design very compact and simple is described. It is shown that this scheme is general, simple, and safe. It provides a structure that can contain all components of a digital VLSI system, including static, dynamic, and precharged logic as well as memories and PLAs. Clock and data signals are presented in a clean way that makes VLSI circuits and systems well suited for design compilation. >

A unified single-phase clocking scheme for VLSI systems

A dynamic logic circuit with reduced charge leakage includes a dynamic complementary MOSFET logic circuit with a P-type MOSFET, a number of N-type MOSFETs and a static CMOSFET inverter circuit. In response to a low clock signal, the P-type MOSFET turns on and charges the precharge node to a precharged node voltage. Some of the N-type MOSFETs are interconnected to form a logic circuit to logically process incoming logic signals and in accordance therewith selectively provide a conduction path for electrical charges from the precharge node. In response to a high clock signal, another N-type MOSFET turns on and together with the logic circuit conditionally discharges the precharge node via the logic circuit conduction path to a discharged node voltage. The value of the discharged node voltage is intermediate to the precharged node voltage and the circuit reference node voltage (e.g. VSS=0). The inverter circuit inverts and buffers the precharged and discharged node voltages. In one embodiment, a bias voltage source, connected between the N-type discharge MOSFET and the reference node, provides a bias voltage which is intermediate to the precharged and reference node voltages, and the discharged node voltage is approximately equal to the bias voltage. In another embodiment, a pull-up MOSFET is connected to the discharge MOSFET for selectively providing a pull-up voltage which is intermediate to the precharged and reference node voltages, and the discharged node voltage is approximately equal to the pull-up voltage.

Dynamic logic circuit with reduced charge leakage

A static logic circuit with improved output signal levels includes a static complementary MOSFET circuit with a signal node and pull-up and pull-down amplifiers, each with at least one biasing circuit, connected thereto. The pull-up and pull-down amplifiers are connected to VDD and VSS, respectively, and receive one or more logic signals (e.g. one for an inverter and more for logic gates such as AND, OR, etc.) and one or more bias signals and in accordance therewith provide pull-up and pull-down voltages, respectively, to the signal node. In accordance with the applied pull-up or pull-down voltage, the signal node charges to a charge state with an associated node voltage approximately equal to VDD or VSS, respectively. Each biasing circuit receives the same input logic signal as its associated pull-up or pull-down amplifier and provides thereto a bias signal approximately equal to VSS or VDD, respectively. In accordance with its input logic signal, each pull-up or pull-down amplifier together with its associated biasing circuit provides either an active current path between the signal node and VDD or VSS for applying the desired pull-up or pull-down voltage, respectively, or a leakage current path between VDD and VSS for preventing the application of an undesired pull-down or pull-up voltage during application of the desired pull-up or pull-down voltage, respectively.

Static logic circuit with improved output signal levels

A dynamic clocked inverter latch with reduced charge leakage includes a first node biasing circuit with a P-MOSFET and an N-MOSFET totem-pole-coupled between VDD and an output node, and a second node biasing circuit with another N-MOSFET and another P-MOSFET totem-pole-coupled between the output node and VSS. The first P-MOSFET receives an input data signal and the first N-MOSFET receives a clock signal and in accordance therewith together cause the output node to charge to a charged state having a charge voltage associated therewith. The second N-MOSFET also receives the input data signal while the second P-MOSFET receives the inverse of the clock signal and in accordance therewith together cause the output node to discharge to a discharged state having a discharge voltage associated therewith. During inactive states of the clock signal, the first N-MOSFET becomes reverse-biased by the output node discharge voltage, while during inactive states of the inverse clock signal, the second P-MOSFET becomes reverse-biased by the output node charge voltage, thereby virtually eliminating charge leakage to and from the output node, respectively.

Dynamic clocked inverter latch with reduced charge leakage

Some CMOS circuit techniques, based on a true single-phase clock, where the clock is never inverted, are described. Single-phase dynamic logic and single-phase precharge logic circuits are considered. The advantage of this approach is simple and compact clock distribution and high speed. The high-speed possibility was demonstrated with a binary divider. A clock frequency of 160 MHz was achieved when only standard transistors in a 3- mu m CMOS process were used. The single-phase clock is relatively insensitive to clock rise time, clock fall time, and clock skew. >

I. Karlsson

Papers

True single phase clock dynamic CMOS circuit technique