In this paper, we present a case study of our chip prototype of a 16-node 4×4 mesh NoC fabricated in 45nm SOI CMOS that aims to simultaneously optimize energy-latency-throughput for unicasts, multicasts and broadcasts. We first define and analyze the theoretical limits of a mesh NoC in latency, throughput and energy, then describe how we approach these limits through a combination of microarchitecture and circuit techniques. Our 1.1V 1GHz NoC chip achieves 1-cycle router-and-link latency at each hop and energy-efficient router-level multicast support, delivering 892Gb/s (87.1% of the theoretical bandwidth limit) at 531.4mW for a mixed traffic of unicasts and broadcasts. Through this fabrication, we derive insights that help guide our research, and we believe, will also be useful to the NoC and multicore research community.

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Approaching the theoretical limits of a mesh NoC with a 16-node chip prototype in 45nm SOI

Scaling trends of logic, memories, and interconnect networks lead towards dense many-core chips. Unfortunately, process yields and reticle sizes limit the scalability of large single-chip systems. Multi-chip systems break free of these areal limits, but in turn require enormous chip-to-chip bandwidth. The "macrochip" concept presented here integrates multiple many-core processor chips in a single package with silicon-photonic interconnects. This design enables a multi-chip system to approach the performance of a single large die. In this paper we propose three silicon-photonic network designs that provide low-power, high-bandwidth inter-die communication: a static wavelength-routed point-to-point network, a "two-phase" arbitrated network, and a limited-connectivity point-to-point network. We also adapt two existing intra-chip silicon-photonic interconnects: a token-ring-based crossbar and a circuit-switched torus. We simulate a 64-die, 512-core cache-coherent macrochip using all of the above networks with synthetic kernels, and kernels from Splash-2 and PARSEC. We evaluate the networks on performance, optical power and complexity. Despite a narrow data-path width compared to the token-ring or torus, the point-to-point performs 3.3x and 3.9x better respectively. We show that the point-to-point is over 10x more power-efficient than the other networks. We also show that, contrary to electronic network designs, a point-to-point network has the lowest design complexity for an inter-chip silicon-photonic network.

Silicon-photonic network architectures for scalable, power-efficient multi-chip systems

We present circuits for driving long on-chip wires through a series capacitor. The capacitor improves delay through signal pre-emphasis, offers a reduced voltage swing on the wire for low energy without a second power supply, and reduces the driven load, allowing for smaller drivers. Sidewall wire parasitics used as the series capacitor improve process tracking, and twisted and interleaved differential wires reduce both coupled noise as well as Miller-doubled cross-capacitance. Multiple drivers sharing a target wire allow simple FIR filters for driver-side pre-equalization. Receivers require DC bias circuits or DC-balanced data. A testchip in a 180 nm, 1.8 V process compared capacitively-coupled long wires with optimally-repeated full-swing wires. At a 200 mV swing, we measured energy savings of 3.8x over full-swing wires. At a 50 mV swing, we measured energy savings of 10.5x. Throughput on a 14 mm wire experiment due to capacitor pre-emphasis improved 1.7x using a 200 mV swing.

High Speed and Low Energy Capacitively Driven On-Chip Wires

This paper introduces an approach to dc power delivery that reduces power loss by minimizing redundant energy conversion. Existing power distribution techniques tend to increase the number of cascaded conversion stages, which limits overall efficiency. Differential power processing enables independent load regulation, while processing only a small portion of the total load power. Bulk power conversion occurs once. Load voltage domains are connected in series, and differential converters act as controllable current sources to regulate intermediate nodes. This enables independent, low supply voltages, which can reduce system energy consumption, especially in digital circuits and solid-state lighting. Since differential voltage regulators process a fraction of the load power, decreased size, cost, and conversion losses are attainable. Under balanced load conditions, secondary differential converters do not process any power. This paper analyzes several differential power delivery architectures that can be applied to homogenous and heterogeneous loads at various levels: chip, board, blade, etc. A variety of operating conditions for a test system with four series voltage domains are examined in simulation and verified with experimental hardware. Results in a reference application show a 7–8% decrease in input power and 6–7 percentage points increase in overall conversion efficiency as compared to a conventional cascaded approach.

Differential Power Processing for DC Systems

As technology scales, SoCs are increasing in core counts, leading to the need for scalable NoCs to interconnect the multiple cores on the chip. Given aggressive SoC design targets, NoCs have to deliver low latency, high bandwidth, at low power and area overheads. In this paper, we propose Single-cycle Multi-hop Asynchronous Repeated Traversal (SMART) NoC, a NoC that reconfigures and tailors a generic mesh topology for SoC applications at runtime. The heart of our SMART NoC is a novel low-swing clockless repeated link circuit embedded within the router crossbars, that allows packets to potentially bypass all the way from source to destination core within a single clock cycle, without being latched at any intermediate router. Our clockless repeater link has been proven in silicon in 45nm SOI. Results show that at 2GHz, we can traverse 8mm within a single cycle, i.e. 8 hops with 1mm cores. We implement the SMART NoC to layout and show that SMART NoC gives 60% latency savings, and 2.2X power savings compared to a baseline mesh NoC.

SMART: a single-cycle reconfigurable NoC for SoC applications

Capacitively-driven on-chip wires reduce both latency and energy compared to repeaters. A series coupling capacitance offers preemphasis to lower wire delay, reduces the driven load, and lowers the wire voltage swing without a second power supply. A 0.18mum CMOS testchip shows 10.5times energy savings at a 50mV swing compared to full-swing repeated wires, and a 3times gain in wire bandwidth

I. Ono

Papers

High-Speed and Low-Energy Capacitively-Driven On-Chip Wires