For reasons of economy and flexibility, BISDN (Broadband Integrated Services Digital Network) is expected to replace existing application-oriented communication networks. ATM (Asynchronous Transfer Mode) is a high-speed packet-switching technique that has emerged as the most promising technology for BISDN. Since early 1980s, a large number of architectures have been proposed for ATM switching. In this paper, we present a descriptive survey of ATM switch architectures, with emphasis on electronic space-division point-to-point switches.

Survey of ATM switch architectures

The paper presents a new cell switching architecture for ATM-based networks. The proposed helical switch is a multistage interconnection network which implements the self-routing technique with efficient buffer sharing. Although the switch may route cells along multiple paths, the connection-oriented mode required by the ATM-based network is supported. Cell sequence integrity is guaranteed by introducing a virtual helix which forces cells routed along different paths to proceed in order and fill the internal buffers uniformly. The performance of the helical switch is investigated under uniform and nonuniform traffic patterns. Unlike single-path multistage networks such as buffered banyan networks which can degrade significantly under nonuniform traffic, the helical switch is shown to be quite robust with respect to nonuniform traffic conditions. >

The helical switch: a multipath ATM switch which preserves cell sequence

The authors present a queuing analysis and a simulation study of banyan switch fabrics based on 2*2 switching elements with crosspoint buffering. In particular, the results apply to the PHOENIX switching element based banyan fabrics. The results indicate that crosspoint buffering provides throughput approaching the offered load under uniform traffic conditions. The effect of bursty traffic on the performance of the switch is studied. It is shown that a speedup factor of three or more is required to achieve acceptable delay and packet loss probability. It is also shown that the amount of buffer space required per port increases linearly with the burst size for a desired packet loss performance. For a given burst size the packet loss rate decreases exponentially as the buffer size is increased. The impact of crosspoint buffering and shared buffering in the switching elements on the performance of the banyan fabric is analyzed. >

Performance of a crosspoint buffered ATM switch fabric

This paper presents a new self-routing packet network called the plane interconnected parallel network (PIPN). In the proposed design, the traffic arriving at the network is shaped and routed through two banyan network based interconnected planes. The interconnections between the planes distribute the incoming load more homogeneously over the network. The throughput of the network under uniform and heterogeneous traffic requirements is studied analytically and by simulation. The results are compared with the results of the baseline network and another banyan network based parallel interconnection network. It is shown that, for the proposed design, a higher degree of heterogeneity results in better performance.

Design and performance evaluation of a banyan network based interconnection structure for ATM switches

A novel cell switching architecture for asynchronous transfer mode (ATM)-based networks is presented. The proposed helical switch is a multistage interconnection network which implements the self-routing technique with efficient buffer sharing. Although the switch may route cells along multiple paths, the connection-oriented mode required by the ATM-based network is supported. Cell sequence integrity is guaranteed by introducing a virtual helix which forces cells routed along different paths to proceed in order and fill the internal buffers uniformly. Under a uniform traffic pattern, it is shown that the minimum achievable throughput is 5/6 per output line. >

A report is presented on a queueing analysis and a simulation study of a switch fabric based on a buffered banyan structure whereby buffers are placed at the output links of each switching element. When buffers are located at the input links, it is well known that maximum throughput is limited to approximately 0.45 under a uniform input traffic pattern. This bottleneck is due to the head of the line (HOL) contention at each switching element and is intrinsic to input queueing. The authors propose a buffered banyan switch built from smaller knockout switches which are output-buffered switches. With small knockout switches as the basic switching elements, the complexity of the overall switch fabric is manageable and no internal clock speedup is required. Furthermore, it is shown that with the proposed output-buffered banyan switch, a maximum throughput of 1 can be achieved. >

I. Widjaja

Papers

Performance of output-buffered banyan networks with arbitrary buffer sizes