Disclosed is a method of manipulating the rate of upper gastrointestinal transit of a substance in a mammal Also disclosed are methods of manipulating satiety and post-prandial visceral blood flow A method of treating visceral pain or visceral hypersensitivity in a human subject is also described A method for prolonging the residence time of an orally or enterally administered substance by promoting its dissolution, bioavailability and/or absorption in the small intestine is also described These methods are related to a method of transmitting to and replicating at a second location in the central nervous system a serotonergic neural signal originating at a first location in the proximal or distal gut of a mammal and/or a method of transmitting to and replicating at a second location in the upper gastrointestinal tract a serotonergic neural signal originating at a first location in the proximal or distal gut

Methods for manipulating upper gastrointestinal transit, blood flow, and satiety, and for treating visceral hyperalgesia

A caching input/output hub includes a host interface to connect with a host. At least one input/output interface is provided to connect with an input/output device. A write cache manages memory writes initiated by the input/output device. At least one read cache, separate from the write cache, provides a low-latency copy of data that is most likely to be used. The at least one read cache is in communication with the write cache. A cache directory is also provided to track cache lines in the write cache and the at least one read cache. The cache directory is in communication with the write cache and the at least one read cache.

Distributed read and write caching implementation for optimized input/output applications

A semiconductor integrated circuit has a central processing unit and a rewritable nonvolatile memory area disposed in an address space of the central processing unit. The nonvolatile memory area has a first nonvolatile memory area and a second nonvolatile memory area, which memorize information depending on the difference of threshold voltages. The first nonvolatile memory area has the maximum variation width of a threshold voltage for memorizing information set larger than that of the second nonvolatile memory area. When the maximum variation width of the threshold voltage for memorizing information is larger, since stress to a memory cell owing to a rewrite operation of memory information becomes larger, it is inferior in a point of guaranteeing the number of times of rewrite operation; however, since a read current becomes larger, a read speed of memory information can be expedited. The first nonvolatile memory area can be prioritized to expedite a read speed of the memory information and the second nonvolatile memory area can be prioritized in guaranteeing the number of times of rewrite operation of memory information more.

Semiconductor Integrated circuit

A method and system for font building by providing for the downloading of a subset of glyphs at a client device from a server. The subset can include one or more particular requested glyphs. The subset is accompanied by one or more further glyphs determined by selection criteria, which can include: frequency of use of the glyphs in a particular language; frequency of use of the glyphs by at least one client device; and relationships between particular glyphs.

Method and arrangement for font building

A variable-length encode/decode processor (11) includes a central processing unit (16) and an instruction buffer (32) and a GETBITS processing engine (18) coupled to the central processing unit (16). The processor (11) can be used to encode data as variable-length symbols or to decode variable-length symbols usedin MPEG protocols.

Processing circuit and method for variable-length coding and decoding

It is to realize a function clock generation circuit with which a wiring area and cell area, and further a power consumption can be reduced, and a timing design is easy. An input terminal D of a through latch circuit LTC11 is connected to an input line of an enable signal EN, an inversion clock input terminal G is connected to the input line of the clock signal, one input terminal of a NAND gate NAND11 is connected to an output terminal Q of a through latch circuit LTC11, the other input terminal is connected to the input terminal of the clock signal CK, and the output terminal is connected to the input terminal of an inverter INV11. Then, in the through latch circuit LTC11, the enable signal EN is sampled at the rising edge of the clock signal CK, and according to the value, the clock pulse immediately after the sampling is passed or blocked by the logical gate LGT comprising a NAND gate NAND11 and an inverter INV11.

Function clock generation circuit and D-type flip-flop equipped with enable function and memory circuit using same

A bus emulation apparatus includes serial transfer paths, serial interface circuits having a parallel to serial conversion circuit for converting parallel data from a peripheral circuit to serial data and supplying to a serial transfer path and a serial to parallel conversion circuit for converting serial data from a hub circuit to parallel data and supplying to a peripheral circuit, a hub circuit for supplying serial data from a serial interface circuit to a serial interface circuit connected to a peripheral circuit as a transfer destination of said parallel data among the serial interface circuits, and a network for connecting them, and installed on an LSI or a print circuit board to replaced a parallel bus.

Bus emulation apparatus

A synchronizing circuit including a plurality of latches, comprised of a first dynamic type through latch circuit and a second dynamic type through latch circuit between which is disposed a static type through latch circuit, the circuits connected in cascade. Data is sampled at the timing of the rising edge of the clock signal generated by a pulse generation circuit connected to a clock input circuit and data is output at the timing of the trailing edge. By defining the clock pulse width generated at the pulse generation circuit larger than the clock skew, it is possible to prevent malfunctions of the LSI caused by clock skew caused by deviation of timing of the clock distribution. Moreover, by providing a dynamic type through circuit for a scan test input to the first dynamic type through latch circuit in parallel, a scanning function can be realized and a malfunction due to the clock skew during scanning can be prevented.

Synchronizing circuit with dynamic and static latch circuitry

A delay circuit is constituted by connecting a
plurality of delay elements in series, each delay
element is constituted by a pMOS transistor P1 and a
nMOS transistor N1 having a larger driving capability
than P1 and by a nMOS transistor N2 and a pMOS
transistor P2 having a larger driving capability than
N2, an input signal is applied to the gate of the
transistor P1, a precharge signal is applied to the
gate of the transistor N1. an inverted signal of the
precharge signal is applied to the gate of the
transistor P2, the gate of the transistor N2 is
connected to an intermediate node A, an input signal
S IN is input to each delay element as the precharge
signal, and when the input signal S IN is at a high
level, the node A is in the state of a low level and
the output terminal OUT is in the state of a high
level, the falling edge of the input signal S IN is
sequentially propagated by delay elements, and thus a
delay signal is obtained.

Delay circuit and oscillator circuit using the same

A digital DLL circuit includes: a first register configured to hold a first delay specifying value to specify a delay of a rising edge side of a signal; a second register configured to hold a second delay specifying value to specify a delay of a falling edge side of a signal; and a digitally-controlled variable delay circuit configured to be allowed to individually control delays of a rise side and a fall side of a signal. The digital DLL circuit further includes a control circuit configured to implement control so that a rise-side delay and a fall-side delay by the variable delay circuit are kept at the first delay specifying value of the first register and the second delay specifying value of the second register, respectively.

Ichiro Kumata

Papers

Function clock generation circuit and D-type flip-flop equipped with enable function and memory circuit using same

Bus emulation apparatus

Synchronizing circuit with dynamic and static latch circuitry

Delay circuit and oscillator circuit using the same

Digital DLL circuit