PROBLEM TO BE SOLVED: To provide a system for indicating a position of an electrical distribution device configured to be racked into an electrically connected condition within an enclosure and racked out to an electrically disconnected condition via a racking mechanism. SOLUTION: The system is provided with: a rotating indicator consisting of an indicator drum 42 having a first position 48 indicating the connected condition and a second position 50 indicating the disconnected condition, the indicator operably connected to the racking mechanism to rotate the indicator in response to movement of the racking mechanism between the connected condition and the disconnected condition. The system is also provided with a biasing device 46 for biasing rotation of the indicator toward the first position when the racking mechanism is in the connected condition and biasing rotation of the indicator toward the second position when the racking mechanism is in the disconnected condition. The system is further provided with a first mechanical stopper 76 for holding the indicator at the first position when the racking mechanism is in the connected condition, and a second mechanical stopper for holding the indicator at the second position when the racking mechanism is in the disconnected condition. COPYRIGHT: (C)2010,JPO&INPIT

System and method for indicating position of electrical distribution device

PROBLEM TO BE SOLVED: To provide a semiconductor logical apparatus with reduced electric power consumption and with an ability to obtain precisely transferred data without omission. SOLUTION: Data input to a data retainer 2 is retained in an address specified depending on a counted value of a counter 13. On the other hand, data output from a data output section 3 are read out from an address specified depending on a counted value of a counter 21. A reset process is applied to the counter 13 in parallel with a rise of a data enabling signal, while a reset process is applied to the counter 21 in parallel with a rise of a signal produced by delaying the data enabling signal by a given time through a delay circuit 4. Due to the application of the delay process implemented by the delay circuit 4, input data have been already determined at the time of giving reading-out instruction, thus allowing data to be correctly transferred. COPYRIGHT: (C)2007,JPO&INPIT

Semiconductor logical apparatus and electronic apparatus equipped therewith

PURPOSE:To eliminate the need for a delay circuit with large scale even when a high speed logic element is employed by selecting the width of a clock signal larger than the sum between a clock signal skew DELTAt and a holding time th of the post-stage FF CONSTITUTION:A delay circuit 31 is connected between the output of a FF 12 and an input of a FF 14 When a clock signal 18 descends, an input signal (data D1) 11 is inputted to the FF 12 at a point of time t1, an output signal 19 is obtained and a P-channel transistor (TR) 32 is turned off by the clock signal 18 inputted to the delay circuit 31 at the same time and an N-channel TR is turned off Thus, the output signal 22 of the delay circuit 31 holds a level (data D0) just before the clock signal 18 descends When a clock signal rises, a level (data D1) of the output signal 19 is outputted inversely at a point of time t2 as a delay output signal 22 and set to the FF 14 at the fall of the next clock signal 21 Thus, the output signal of the FF 12 is delayed by the clock pulse width, the holding time th is satisfied to guarantee the normal circuit operation Thus, the delay of the clock signal width is obtained always and the circuit is constituted by the prescribed number of elements independently of the holding time th

Ikeda Katsuji

Papers

Flip-flop logic circuit