A microcontroller capable of improving processing performance as a whole by executing different programs by a plurality of CPUs and capable of detecting abnormality for safety-required processing by evaluating results of the same processing executed by the plurality of CPUs. A plurality of processing systems including CPUs and memories are provided, data output from the CPUs in each of the processing systems is separately compressed and stored by compressors for each of the CPUs, respectively. The compressed storage data is mutually compared by a comparator, and abnormality of processing can be detected when the comparison result indicates a mismatch. Even when the timings by which the same processing results are obtained are different when the plurality of CPUs asynchronously execute the same processing, the processing results of both of them can be easily compared with each other since compression is carried out by the compressors. Moreover, since the comparison of the comparator is enabled when comparison enable is given from all the CPUs, the comparison operation result can be obtained based on the timing at which the results of compression by the plurality of compressors are determined.

Multi-core microcontroller having comparator for checking processing result

PROBLEM TO BE SOLVED: To change screen displays at the time of ordering and of getting a complete set of products, to reduce processing time by reducing errors in each operation and to simplify a stock management. SOLUTION: An input of a total key or a sub-total key is determined (S1) after registering merchandise having a main code and a sub code, it is determined whether there is merchandise of an identical main code or not after an input is made (S2), and the total number of merchandise of the identical main code and the name of the merchandise set on the main code are displayed (S3). When there is no input of the total key or the sub total key at a processing S1 or when there is no merchandise of the identical main code at a processing S2, a name of the merchandise set so that the main code of the merchandise and the sub code coincide to each other is displayed (S4). It is determined that a processing of a merchandise registration is completed (S5). A display method of a processing S3 and a processing S4 is changed from the time of getting a complete set of merchandise to the time of registration and a display of a work efficiency in accordance with an operation condition is made.

Electronic cash register

Faul allowable memory array

PURPOSE:To detect and correct an error generated in a frame converting memory at the time of converting digital data into a frame by means of simple constitution. CONSTITUTION:The phase of input data 10 is successively shifted by respective delay circuits 111, 112 and phase-shifted contents are written in memories 101 to 103 at the same timing. Data stored in the memories 101 to 103 are read out at the same timing add the phases of respective read data are corrected by respective delay circuits 113, 114 so as to coincide with each other. A majority value among data 20 to 22 having a coincident phase is determined by a majority circuit 121 and outputted as output data 31.

Error correcting circuit

Data display system

PURPOSE:To reduce the mutual effect of two asynchronous pulses, by simultaneously operating both systems through the use of the clock pulse from one system, in a circuit operated with the two clock pulses. CONSTITUTION:A DA converter 1 is operated with a clock pulse CLB and a holding circuit 3, a filter 2, an AD converter 1' and a filter 2' in the DA conversion system being other circuits are all operated with a clock pulse CLA. A timing circuit 4 taking a timing changing the output is connected to the DA converter 1 and the said timing circuit 4 is connected to a control circuit 5 operating the holding circuit 3 with the clock pulse CLA. Further, the holding circuit 3 is connected to another timing circuit 6 to which the clock pulse CLA is inputted, and the filters 2 and 2' and the AD converter 1' are operated with the said timing circuit 6 with the clock pulse CLA.

Clock converting circuit

PURPOSE:To improve yield of an ROM by determining an output value of >=3 ORMs of the same kind basing on judging criteria and making them usable as a complete ROM. CONSTITUTION:ROMs 5-7 store data of the same contents and the contents of address are also the same. When characterwise addresses A11-AN are given to ROMs 5-7 and addresses of dots in characters A1-A10 are given, 0 or 1 of the same contents is outputted. Decision by majority is made by a majority circuit 8, and outputted as output of one ROM. When there are defects, whichever greater in number out of 0 or 1 is selected by the circuit 8, and therefore, defects are compensated. As it rarely occurs that two ROMs have defective cell at the same position, three defective ROMs can be used as one prefect ROM. Thus, yield can be improved.

Reading system for read only memory device

PURPOSE:To obtain the small capacity of a memory and to facilitate circuit integration by making compressed data and coefficient for the data one word and writing in a memory. CONSTITUTION:A data compressing circuit 11 compresses input data of, for instance, 14-16 bits of linear encoded digital sound signals applied to a terminal 31 to 8 bits according to companding rule such as A rule or mu rule etc., or converts the data to ADPCM signals of 4 bits. Address signals and write pulse are applied to terminals 34, 35 from a control circuits, and compressed data selected by a selector 14 and a coefficient selected by a selector 15 are written in an area of a memory 16 designated by an address signal as one word. Read compressed data are set to a register 17 and then applied to a data expanding circuit 20, and at the same time, applied to a register 19. Compressed data set to the register 19 is applied to the memory through the selector 14, and written according to an address signal at the time of a write mode.

Filter arithmetic control system

PURPOSE:To obtain a quickly operating DPCM encoder, by providing a quantizator, delay element, multiplier, and 3-input and 2-output digital-digital converter. CONSTITUTION:The DPCM signal of the output of a quantizator 3 is inputted by inversion in a 3-input and 2-output DD converter 7 after it is multiplied by a forecasting coefficient of 1/2 by a multiplier 9. Moreover, the value of 1-sampling period before which is the output of an FF 6 is inputted by inversion in the converter 7 after it is multiplied by the forecasting coefficient of 1/2 by another multiplier 10. Two output signals are obtained from the two inputs of the converter 7 and a PCM signal and sent to an adder 8. The added result of the adder 8 is supplied to the quantizator 3 after delaying the result through an FF 2 and the DPCM signal is outputted from the quantizator 3. Since the operating speed of this encoder depends upon the FF 6, quantizator 3, multiplier 10, and converter 7, high-speed processing can be realized.

High-speed dpcm encoder

PURPOSE:To reduce the set-up time and the holding time of both data and timing signals by using a low-speed clock undergone the time shaping to a master clock to give the time shaping to both signals. CONSTITUTION:Both data and timing signal inputs API and APSY are read by a low-speed clock PCK and turned into a low-speed data signal output PI 1 and a low-speed timing signal output SY 1 respectively. The clock PCK undergoes the time shaping by a master clock MCK through an FF 12 and is turned into a clock PPCK. The both signals PI 1 and PY 1 undergo the time shaping through an FF 13 and an FF 14 respectively by the signal PPCK. Thus the data and timing signal outputs PI2 and SY2 are obtained. Then both signals APSY and API are readby the clock PCK and therefore both the holding time and the set-up time can be increased.

Ikezawa Masuyuki

Papers

Clock converting circuit

Reading system for read only memory device

Filter arithmetic control system

High-speed dpcm encoder

Input circuit for data signal and timing signal