A low-cost, moderate performance small computer system is provided by allowing a single sharable block of memory to be independently accessible as graphics or main store memory. Allocation of the memory is selected programmably, eliminating the need to have the maximum memory size for each block simultaneously. Performance penalties are minimized by dynamically allocating the memory bandwidth on demand rather than through fixed time slices. A reallocatable memory subsystem enables transparent transfer of memory function of a lower-performance memory such as DRAM to occur in conjunction with a memory upgrade to a higher-performance memory such as VRAM, for example.

Method and apparatus for allocating display memory and main memory employing access request arbitration and buffer control

The present invention provides a hard drive accelerating system (32) that substantially improves the hard disk data transfer speed in a computer. The accelerating system decomposes a traditional CPU IO command to read or write a hard disk drive (18) into two separate tasks that can be executed concurrently. A read buffer (40) and a write buffer (42) are used to link the two tasks. A state machine (48) generates consecutive IO read cycles to fetch data from the hard drive to the read buffer while the CPU executes IO commands to retrieve data from the read buffer. A programmable hardware register (49) adjusts the hard disk IO cycle time to achieve maximum compatibility with different hard drive speeds.

Hard disk accelerating system for computer

An IC card with a bus structure switchable between a narrow bus mode (such as an 8 bit bus) and a wide bus mode (such as a 16 bit bus). A plurality of memories are provided (in the example preferably 8 bit memories). Addresses are coupled to the IC card for activating the memories in parallel when in the wide bus mode or in selectable sequence when in the narrow bus mode. The data lines of the memories are connected by bus switching means to couple the memory data lines to the output bus so that data exchange is in parallel between both of the memories and the 16-bit bus in the wide bus mode, and is between individual ones of the memories and only the 8-bit bus in the narrow bus mode. The result is efficient use of both semiconductor memories in both the wide bus and narrow bus modes, with automatic switching between modes on the IC card in dependence upon a logic signal derived from the external terminal which defines the mode in which the IC card is intended to operate.

IC card with switchable bus structure

A plurality of data processor units (11, 16 17) are connected to a common bus (10) which is connected to first and second interleaved storage units (1, 2). The system is a synchronous one in which timing means (23) establish a series of information transfer intervals (t0-t7, etc.). One or more of the processors units (16, 17) contain apparatus for selectively commencing an address transfer on the bus (10) to one of the storage units (1, 2) during a transfer interval; the storage transaction initiated by the address transfer will require more than the one transfer interval to complete. One or more of the processors (16. 17) have means (3, 4) for monitoring the bus (10) in order to determine whether an address on the bus has been transferred to the first or the second storage unit (1.2) during a particular transfer interval. The address transfer apparatus further includes apparatus (50) responsive to the monitoring apparatus for selectively transferring the next subsequent address to the other of said storage units (1, 2) to thus achieve alternating interleaving between storage units (1, 2).

Data processing system with a plurality of processors accessing a common bus to interleaved storage

A bus system wherein N-bit devices (12b,12c) attached to the lower half (30L) of a 2N-bit bus (30) communciate with 2N-bit (12a, 12d) devices attached to the full bus. Bi-directional registered transceivers (60,62,65,67) are coupled between the upper and lower halves of the bus. The N-bit devices are capable of asserting a pair of signals called HOLDN and LATCHN. For a 2 N-bit source device transmitting data to an N-bit sink device, the 2 N-bit source puts 2 N bits of data on the upper and lower halves of the bus during a given cycle, during which the N-bit sink device samples the N bits on the lower half of the bus. The assertion of HOLDN causes the N bits on the upper half of the bus to be latched and subsequently driven onto the lower half of the bus. Where an N-bit source device is communicating to a 2 N-bit sink device, the N-bit device puts the high order N bits and low order N bits of data on the lower half of the bus on successive cycles. During the cycle that the high order bits are on the bus, the N bit source device asserts LATCHN which causes the data to be latched and then driven onto the upper half of the bus during the subsequent cycle,

Transparent data bus sizing

An N-bit (e.g. N = 4) memory (24) has separately accessible portions (A and B) which may be odd addresses and even addresses respectively. The even portion (B) is coupled by read and write buffers (21, 23) to two N-bit data buses (11,12) respectively so that one bus (11) is a read bus and the other (12) is a write bus for N-bit read/write operations. The odd portion (A) is coupled by read and write buffers (20, 21) and multiplexers (18, 19) controlled by a mode signal (13) so that for an N-bit data mode again the one bus (11) is a read bus and the other (12) is a write bus. For a 2N-bit mode, the one bus (11) is a write bus for the odd portion (A) and the other bus (12) is a read bus. In the N-bit mode the least significant address bit (16) selects the odd or even buffers. The other address bits (17) access both memory portions (A and B) for simultaneous reading or writing of 2N-bit data via both buses (11 and 12). In an alternative one memory portion is connected solely to one bus for both read and write. The other portion is connected to this bus in the N-bit mode and to the other bus in the 2N-bit mode.

Ikutaro Wako

Papers

Information processing unit