A circuit is configured to be mounted on a memory module connectable to a computer system so as to be electrically coupled to a plurality of memory devices on the memory module. The memory module has a first number of ranks of double-data-rate (DDR) memory devices activated at least in part to a first number of chip-select signals. The circuit is configurable to receive address signals and a second number of chip-select signals from the computer system. The circuit is further configurable to generate and transmit phase-locked clock signals to the first number of ranks, and to generate the first number of chip-select signals in response at least in part to the phase-locked clock signals, the address signals, and the second number of chip-select signals.

Multirank DDR memory modual with load reduction

A memory module includes a plurality of memory devices and is operable in a computer system to perform memory operations in response to memory commands from a memory controller of the computer system. The memory module comprises a register device configured to receive a set of input control/address signals associated with a respective memory command (e.g., a read command or a write command) from the memory controller and to generate a set of output control/address signals in response to the set of input control/address signals. The set of output control/address signals are provided to the plurality of memory devices. The memory module further comprises a circuit to selectively isolate one or more first memory devices among the plurality of memory devices from the memory controller in response to the respective memory command so as to reduce a load of the memory module to the computer system while one or more second memory devices among the plurality of memory devices are communicating with the memory controller in response to the set of output control/address signals.

Memory module with load reducing circuit and method of operation

A memory module operable to communicate data with a memory controller via a data bus comprises a plurality of memory integrated circuits including first memory integrated circuits and second memory integrated circuits, a data buffer coupled between the first memory integrated circuits and the data bus, and between the second memory integrated circuits and the data bus, and logic coupled to the data buffer. The logic is configured to respond to a first memory command by providing first control signals to the data buffer to enable communication of at least one first data signal between the first memory integrated circuits and the memory controller through the data buffer, and is further configured to respond to a second memory command by providing second control signals to the data buffer to enable communication of at least one second data signal between the second memory integrated circuit and the memory controller through the data buffer.

Memory module with data buffering

PROBLEM TO BE SOLVED: To provide a display 10 for an automobile for suppressing reflection which lowers visibility of a transparent display 11 while keeping high visible light transmittance of the transparent display 11. SOLUTION: The display 10 for the automobile installed in a dashboard 30 of the automobile includes the transparent display 11, and a protection cover 12 installed on a display surface of the transparent display 11 and composed of transparent resin which suppresses scattering of light. An installation angle θ0 of the transparent display 11 is an angle at which the ceiling 40 of the automobile is reflected on the protection cover 12 to be viewed from a driver sitting on a seat 20. COPYRIGHT: (C)2010,JPO&INPIT

Inoue Maki

Papers

Display for automobile