An optical fiber end portion (10) which has a ferrule (11) which comprises a butting end face (11e) opposed to or butted against an optical device (20), and a single fiber hole or a plurality of fiber holes formed in parallel at predetermined intervals, into which one end of optical fiber (13a) is inserted, the optical fiber being optically connected to said optical device, a method for manufacturing the optical fiber end portion, and a construction for connecting the end portion to the optical device. The ferrule is formed of a molded product of synthetic resin, and is provided with at least one connecting member (12) on the side of butting end face connected to the optical device. The connecting member (12) has a linear expansion coefficient set at a value smaller than the linear expansion coefficient of a synthetic resin forming the ferrule.

Multifiber connector, a method of manufacturing the same, and a construction for connecting the multifiber connector to an optical device

An adder-subtracter for signed absolute values wherein two inputs of signed absolute values are operated with circuits based on the two's complement representation and the operated on result is output in the form of signed absolute value. The adder-subtracter executes two kinds of a subtractive operations for inputs in the form of signed absolute values in parallel. One of the operated results should then be selected according to the sign of the subtracted result, and inverted to be output depending on the sign so as to obtain a subtractive result directly in the form of a signed absolute value.

Adder-subtracter for signed absolute values

Provided is a parallel comparison/selection operation device which efficiently makes a search for a maximum value or a search for a minimum value with an index. The parallel comparison/selection operation device is provided with a vector comparison/selection unit (242) which utilizes vector data (1) and vector data (2) and compares elements respectively included in the vector data (1) and the vector data (2) for each of the corresponding elements, selects one element in either the vector data (1) or the vector data (2) on the basis of the result of the comparison, and generates vector data (3) comprising the selected elements; and an index vector selection unit (243) which utilizes an index vector (1) in the vector data (1), an index vector (2) in the vector data (2) and a comparison result vector and selects one element in either the index vector (1) or the index vector (2) on the basis of the comparison result vector, and generates and outputs an index vector (3) comprising the selected elements.

Parallel comparison/selection operation apparatus, processor, and parallel comparison/selection operation method

A method of discovering a fault in a circuit is disclosed. The method comprises generating a first result of a selected function by performing the selected function on an operand, wherein the selected function employs a mask. Once the function is performed, an antimask of the mask is created, and the modulo of the antimask is calculated. A modulo function of the first result of the selected function is calculated to obtain a third result. A modulo of the operand is then calculated to obtain a fourth result, and a second function is then performed on the second result and the third result to obtain a fifth result. In response to comparing the fifth result to the fourth result, a signal is propagated to indicate a fault in the circuit.

Method and system for checking rotate, shift and sign extension functions using a modulo function

An optical fiber terminal (10) for optically connecting an optical fiber and an optical device comprises a ferrule (11) having an abutting end (11e) which faces an optical device (20) or abuts on it and a single fiber hole or a plurality of fiber holes which are arranged in parallel at given pitches and through which the ends of optical fibers are passed and fixed with adhesive. The ferrule is a molded product of synthetic resin. At least one connecting member (12) is provided on the abutting end (11e). The linear expansion coefficient of the connecting member (12) is smaller than that of the synthetic resin constituting the ferrule.

Terminal of optical fiber, method of its manufacture, and structure for connecting the terminal and optical device

PURPOSE:To shorten the arithmetic time and to reduce the quantity of hardware by calculating after separating high-order (M-N) bits in case it is known that the low-order N bits as one side are 0 among two M-bit binary inputs. CONSTITUTION:Binary numbers Y1, X1 and X2 are fed to an absolute value arithmetic circuit 300 containing auxiliary input to produce a full-bit OR C1 of the X2. A decision signal C0 satisfying X1+C1 Y1 is satisfied. While Y1-X1-C1 is calculated in the case of X1+C1<=Y1. Thus the binary numbers Z1 of the result of calculation, i.e., the absolute value of the difference between upper bits of X and Y is delivered. A complement generating circuit 310 delivers the complement X3 of X2 to the circuit 320, and the circuit 320 supplies X2 and X3 and the signal C0 to select the X2 or its complement X3 in accordance with 1 or 0 of the signal C0. This selected X2 or X3 is delivered as a binary number Z2 which means the absolute value of the difference between low-order bits of X and Y.

Arithmetic circuit of absolute value

PURPOSE:To improve the trouble detecting rate of a check circuit by defining the wrong binary data [1, 1, ..., 1] as the modulo value when a trouble is detected in consideration of said wrong binary data [1, 1, ..., 1]. CONSTITUTION:A modulo-3 production circuit 301 has a trouble and the value D=[1, 1] of a modulo-3 is obtained in terms of the sum Z of two binary data X=[0, 1, 1, 0] and Y=[0, 1, 0, 1]. A modulo-3 expected value generating circuit 302 has a trouble and the sum C=[1, 1] is obtained between the values of X and Y modulo-3. An arithmetic circuit part has a trouble and Dnot equal to C is obtained. Then the output M=[1, 1] is obtained due to a trouble of a modulo-3 circuit 303. Then the output M=[1, 1] is obtained in any case of said troubles and therefore it is detected that a circuit preceding the output M has a trouble. Then the value [1, 1] of the modulo-3 showing a trouble is outputted to a check circuit of the following stage. Thus the occurrence of a trouble can be decided with input of the value [1, 1]. In such a way, the error detecting rate of the check circuit is improved.

Modulo-w circuit

PURPOSE:To improve the processing capacity of the whole data processor by simultaneously leading out data in a storage part and a mask bit. CONSTITUTION:When a write indicating signal 1 and writing data 14 are inputted from a writing means 104 to the storage part 101, the storage part 101 stores the writing data in its specified storage element. When a read indicating signal 3 is inputted from a reading means 103 to the storage part 101, the storage part 101 outputs data stored in the storage element to the reading means 103 as reading data 11. When a write indicating signal 2 and writing data 17 are inputted from the writing means 104, a mask register 102 stores the writing data 17 and outputs the stored data to the reading means 103 as mask data 12. The reading means 103 outputs the signal 3 to the storage part 101, selects one mask bit out of the mask data 12 simultaneously with the supply of the data 11 and outputs a reading mask bit 19 and the reading data 11.

Register file device

PURPOSE:To facilitate easy control of a selection signal producing part by defining the data including a bit indicating the validity of the data as a subject of selection CONSTITUTION:For instance, the number (n) of bits is equal to 4 with three data A, B and C Under such conditions, a valid bit selecting circuit 11 supplies the selection information S (=sa, sb, sc) and a valid indication bit ae of data A (=ae, a0, a1, a2) together with a valid indication bit be of data B (=be, b0, b1, b2) and a valid indication bit ce of data C (=ce, c0, c1, c2) Then the circuit 11 outputs a logic equation de=saae+sbbe+scce through a valid indication bit de A data selecting circuit 12 supplies the information S together with bits a0, b0, c0 in said data A-C and valid indication bits ae, be and ce respectively and outputs a bit data d0 with which a logic equation d0=saaea0+sbbeb0+ sccec0 is satisfied

Selection circuit for data processor

PURPOSE:To calculate a vector element section with a usual vector section calculating means and to process the element number by installing plural vector storing means, plural element number storing means, etc. CONSTITUTION:In the calculating system where an element section calculation in a vector with an N number of data as an element and the element and the element number selected at the calculating result are outputted, the first vector storing means 1 outputs a part vector with L number out of N number of elements as an element. The first element number storing means 4 outputs an element number part vector with L number of element corresponding to L elements as an element. An element number part vector corresponding to the part vector stored at the second vector storing means 3 out of outputs of the means 4 is stored in the second element number storing means 5. Thus, the part vector with L number as an element is created, handled as an independent vector and even the element number is handled as an equal vector, thereby executing the calculation between vector elements and processing the element number.

Ishizuka Teru

Papers

Arithmetic circuit of absolute value

Modulo-w circuit

Register file device

Selection circuit for data processor

Vector element section calculating system