An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

A Three Dimensional Structure (3DS) Memory (100) allows for physical separation of the memory circuits (103) and the control logic circuit (101) onto different layers (103) such that each layer may be separately optimized. One control logic circuit (101) suffices for several memory circuits (103), reducing cost. Fabrication of 3DS memory (100) involves thinning of the memory circuit (103) to less than 50 microns in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density inter-layer vertical bus connections (105) are used. The 3DS memory (100) manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques.

Three dimensional structure memory

A lubricating oil composition formulated with a viscosity index (VI) improver composition including a combination of an ethylene α-olefin copolymer having no greater than 66 mass % of units derived from ethylene, and a linear diblock copolymer including at least one block derived primarily from a vinyl aromatic hydrocarbon monomer, and at least one block derived primarily from diene monomer.

Lubricating oil compositions.

To fabricate back side contact pads that are suitable for use in a vertical integrated circuit, vias are made in the face side of a wafer, and dielectric and contact pad metal are deposited into the vias Then the wafer back side is etched until the metal is exposed When the etch exposes the insulator at the via bottoms, the insulator is etched slower than the wafer material (eg silicon) Therefore, when the dielectric is etched off and the metal is exposed, the dielectric protrudes down from the wafer back side around the exposed metal contact pads, by about 8 μm in some embodiments The protruding dielectric portions improve insulation between the wafer and the contact pads when the contact pads are soldered to an underlying circuit In some embodiments, before the contact pads are soldered, additional dielectric is grown on the wafer back side without covering the contact pads In some embodiments, the wafer etch and the fabrication of the additional dielectric are performed one after another by a plasma process while the wafer is held in a non-contact wafer holder In some embodiments, the wafer is diced and the dice are tested before the etch The etch and the deposition of the additional dielectric are performed on good dice only In some embodiments, the dice are not used for vertical integration

Integrated circuits and methods for their fabrication

The Vertical System Integration (VSI) invention herein is a method for integration of disparate electronic, optical and MEMS technologies into a single integrated circuit die or component and wherein the individual device layers used in the VSI fabrication processes are preferably previously fabricated components intended for generic multiple application use and not necessarily limited in its use to a specific application. The VSI method of integration lowers the cost difference between lower volume custom electronic products and high volume generic use electronic products by eliminating or reducing circuit design, layout, tooling and fabrication costs.

Vertical system integration

A surface etchant for silicon comprising an anisotropic etchant containing silicon is disclosed. The etchant provides a textured surface of randomly spaced and sized pyramids on a silicon surface. It is particularly useful in reducing the reflectivity of solar cell surfaces.

Texture etching of silicon: method

A practical photovoltaic module is disclosed which is protected from reverse bias damage and which displays minimal power loss resulting from temporary inoperativeness of one or more individual photovoltaic cells included in the module. The module includes a plurality of series connected photovoltaic cells. Protection from inoperativeness of one or more of these cells is provided with only minimal power loss by providing a reversely poled diode across each of the series connected cells.

Protected photovoltaic module

This disclosure relates to a semiconductor solar energy device which is of the PN-type and utilizes a dielectric anti-reflective coating on the side of the device that faces the sunlight. The fabrication techniques used in making this semiconductor device include the use of a rough or textured pyramid shaped silicon surface beneath the anti-reflective coating to increase solar cell efficiency. Also, ion implantation is used to form the PN junction in the device. The ion implanted region located on the side of the device that is subjected to the sunlight is configured in order to permit metal ohmic contact to be made thereto without shorting through the doped region during sintering of the metal contacts to the semiconductor substrate. The dielectric anti-reflective coating, in one embodiment, is a composite of silicon dioxide and silicon nitride layers. The device is designed to permit solder contacts to be made to the P and N regions thereof without possibility of shorting to semiconductor regions of opposite type conductivity.

Method of semiconductor solar energy device fabrication

A dielectric and conductive isolated island is fabricated by providing an active wafer having a first and a second major surface, a doped region extending from the first surface, and a trench formed at the first surface. A conductive layer is formed on the first surface and in the trench. A planarizable layer comprised of a dielectric layer is then formed on the conductive layer. A handle wafer is bonded to the planarizable layer. The active wafer and the handle wafer are heated so that the doped region diffuses along the conductive layer to form an equalized concentration of dopant along the conductive layer which diffuses into the active wafer to form the doped region adjacent all of the conductive layer. A portion of the second surface of the active wafer is then removed so that at least a portion of the dielectric layer of the planarizable layer is exposed.

Method of making dielectric and conductive isolated island

A PROCESS FOR MAKING THIN SEMICONDUCTOR DEVICES WHEREIN THE SEMICONDUCTOR WAFER STARTING MATERIAL IS INITIALLY LAPPED TO A VERY THIN VALUE. GLASS AND A DUMMY SUBSTRATE ARE THEN SANDWICHED TO THE WAFER FOR FURTHER PROCESSING AND TO PREVENT BREAKAGE OF THE WAFER WHEN SEMICONDUCTOR DEVICES SUCH AS TRANSISTORS ARE CONSTRUCTED THEREIN. THEN THE GLASS AND DUMMY SUBSTRATE ARE REMOVED, LEAVING THIN SEMICONDUCTOR DICE HAVING A VERY LOW THERMAL RESISTANCE TO HEAT EMANATING FROM PN JUNCTIONS THEREIN.

Israel A. Lesk

Papers

Texture etching of silicon: method

Protected photovoltaic module

Method of semiconductor solar energy device fabrication

Method of making dielectric and conductive isolated island

Method for making thin semiconductor dice