An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

An active layer of an NTFT includes a channel forming region, at least a first impurity region, at least a second impurity region and at least a third impurity region therein. Concentrations of an impurity in each of the first, second and third impurity regions increase as distances from the channel forming region become longer. The first impurity region is formed to be overlapped with a side wall. A gate overlapping structure can be realized with the side wall functioning as an electrode.

Semiconductor device and manufacturing method therefor

A high power MOSFET is disclosed in which two laterally spaced sources each supply current through respective channels in one surface of a semiconductor chip which are controlled by the same gate. The channels lead from the source electrodes to a relatively low resistivity region and from there to a relatively high resistivity epitaxially formed region which is deposited on a high conductivity substrate. The drain electrode may be either on the opposite surface of the chip or laterally displaced from and on the same side as the source regions. The epitaxially deposited semiconductor material immediately adjacent and beneath the gate and in the path from the sources to the drain has a relatively high conductivity, thereby to substantially reduce the on-resistance of the device without effecting the breakdown voltage of the device. The breakdown voltage of the device is substantially increased by forming a relatively deep p-type diffusion with a large radius in the n-type epitaxial layer beneath each of the sources.

High power MOSFET with low on-resistance and high breakdown voltage

An accumulation-mode MISFET comprises: a high-resistance SiC layer 102 epitaxially grown on a SiC substrate 101 ; a well region 103 ; an accumulation channel layer 104 having a multiple δ-doped layer formed on the surface region of the well region 103 ; a contact region 105 ; a gate insulating film 108 ; and a gate electrode 110 . The accumulation channel layer 104 has a structure in which undoped layers 104 b and δ-doped layers 104 a allowing spreading movement of carriers to the undoped layers 104 b under a quantum effect are alternately stacked. A source electrode 111 is provided which enters into the accumulation channel layer 104 and the contact region 105 to come into direct contact with the contact region 105 . It becomes unnecessary that a source region is formed by ion implantation, leading to reduction in fabrication cost.

Semiconductor device and method for manufacturing same

A structure containing multiple field-effect transistors (60 and 150) is fabricated from a semiconductor body having material (82) of a specified conductivity type. Semiconductor dopant of the specified conductivity type is introduced, typically simultaneously, (a) into part of a first channel zone of the material of the specified conductivity type to define a threshold channel portion (66) more heavily doped than a main channel portion (65) and (b) into substantially all of a second channel zone of the material of the specified conductivity type. First and second gate electrodes (69 and 141) are provided respectively above, and insulatingly spaced apart from, the first and second channel zones. Semiconductor dopant of the opposit conductivity type is introduced into the semiconductor body to define (a) a pair of first source/drain zones (63/64 and 75/76) laterally separated by the first channel zone and (b) a pair of second source/drain zones (133/134 and 135/136) laterally separated by the second channel zone.

Fabrication of multiple field-effect transistor structure having local threshold-adjust doping

PURPOSE:To produce a MISFET of small on-resistance and high breakdown voltage by disposing an N type layer in adjacent to the N type drain layer of an N type Si substrate and providing the electrode of the same potential as that of the source through an insulation film on the N type layer.

High dielectric strength mis type transistor

PURPOSE:To improve a breakdown voltage and to facilitate a manufacturing process by the constitution in which the polycrystalline Si layer which is formed unitarily with the polycrystalline Si layer as a gate electrode is combined with a drain region CONSTITUTION:The polycrystalline Si layer on a channel part, ie the real gate among gate electrodes is formed by a source-side part 9 of a polycrystalline Si layer 4 and is connected to a drain-peripheral part 10 through high resistance of an intrinsic central part 8 so that it is nearly isolated electrically In this case, if the predetermined drain voltage is applied to a drain region 6 through a contact 16, as the drain-peripheral part 11 of the polycrystalline-Si layer 4 is combined through the capacitance in which a gate insulating film 3 is a dielectric, the potential of the drain-peripheral part 11 increases and produces a depletion layer under the drain-peripheral part 11 Consequently, the depletion layer from the drain region 6 easily extends under the drain-peripheral part 11 Then a junction breakdown voltage is increased and the breakdown voltage of the whole MOSFET can be increased

Mis type semiconductor device

PURPOSE:To decrease input capacity and to improve breakdown resistance voltage by forming a low resistivity second conductive type region on the source side by a self-aligning method, and forming a gate electrode on the region through an insulating film with the surface of a first conductive type well region as a channel part. CONSTITUTION:A P P N type three layer Si substrate is prepared. A thick oxidized SiO2 film 23 is formed on the surface of an N type layer 22. Then, a mask 24, which covers a part of and the drain side of the SiO2 film 23, is formed by photoresist and the like. B is introduced in order to form P type well in the surface of the N layer on the source side. The mask is removed, and e.g. As is deposited and diffused. Thus an N source 25, an N drain 26, and a P well 27 are formed. The insulating film on a source drain contact part is removed. A conductor 30 such as Al is evaporated. The unnecessary part of the Al is removed by photoethcing. Thus a source electrode S, the gate electrode G, and a drain electrode D are formed.

Insulated gate type semiconductor device and manufacture thereof

PURPOSE:To reduce a chip by introducing a one conductive type impurities with a part of a gate electrode provided on a semiconductor substrate as a mask, then introducing reverse conductive type impurities with a part of the same gate electrode as a mask. CONSTITUTION:An n type epitaxial layer 2 is provided on the n type Si substrate 1. The gate electrode 7 is provided via a gate oxide film 6. A central part is covered by a photoresist layer. Then B is implanted with the gate electrode as a mask. A channel region 4 is formed by heat treatment. Then the photoresist is removed, and P is implanted with the gate electrode as a mask again (13 is the implanted region). A source and drain region is formed by heat treatment. In this method, sicne the entire semiconductor region can be formed in a self-aligning mode, the gate length and the channel length can be shortened, and the input capacity can be reduced.

Manufacture of longitudinal type insulated field effect semiconductor device

PURPOSE:To obtain a vertical MOSFET advantageous for preventing electrostatic breakdown by electrically connecting an internal impurity introducing layer to a source and integrally connecting an external impurity introducing layer to a semiconductor gate. CONSTITUTION:Since structure in which an internal N diffusion region 7c surrounded by a looped PN junction is connected to a source electrode and an external N diffusion region 7b is connected to a gate electrode is formed in a back-to-back protective diode using a polycrystal Si layer, the protective diode can be formed at the arbitrary position of the substrate of the MOSFET, size and shape can freely be selected as compared to the case when a slender NPN junction is shaped along the periphery of the substrate as seen in the conventional devices, and a layout is also extremely easy. Electrostatic breakdown can effectively be prevented by forming such a protective diode in parallel between the gate and the source.

Itou Hideshi

Papers

High dielectric strength mis type transistor

Mis type semiconductor device

Insulated gate type semiconductor device and manufacture thereof

Manufacture of longitudinal type insulated field effect semiconductor device

Insulating gate type semiconductor device