A display has a first array of pixels connected to emit individually-controlled amounts of light onto a second array of pixels. The second array of pixels is connected to pass individually-controllable portions of the light. The display has a controller connected to control the pixels of the first and second arrays of pixels. The controller is configured to control the pixels of the first array of pixels to provide on the second array of pixels an approximation of an image specified by image data; determine a difference between the image and the approximation of the image at individual pixels of the second array of pixels; and control the pixels of the second array of pixels to modulate the approximation of the image according to the corresponding determined differences.

High dynamic range display devices

A macroscalar processor architecture is described herein. In one embodiment, a processor receives instructions of a program loop having a vector block and a sequence block intended to be executed after the vector block, where the processor includes multiple slices and each of the slices is capable of executing an instruction of an iteration of the program loop substantially in parallel. For each iteration of the program loop, the processor executes an instruction of the sequence block using one of the slices while executing instructions of the vector block using a remainder of the slices substantially in parallel. Other methods and apparatuses are also described.

Macroscalar processor architecture

A very long instruction word (VLIW) processor exploits program level parallelism as well as instruction level parallelism. Unlike prior VLIW machines which obtain speed advantages using instruction level parallelism, the present processor exploits the parallelism inherent in a VLIW processor by providing new instruction level mechanisms to separate processor execution into parallel threads. This separation allows greater hardware use because more than one program can exploit instruction level parallelism on the system at the same time. A first program and a second program execute concurrently such that the second program executes using resources and cycles that would have been wasted by the first program. This construct is especially useful where the second program is an interrupt service routine because the interrupt service routine can be threaded through the machine with high or low priority while the functional units still process the first program stream. A superscalar version of the processor is also described.

Apparatus and method for program level parallelism in a VLIW processor

Programmable processor and method with wide operations

Processor for executing wide operand operations using a control register and a results register

A method, apparatus, and computer program product for handling IEEE 754 standard exceptions for Single Instruction Multiple Data (SIMD) operations. Each SIMD sub-instruction's corresponding IEEE 754 exception flag 502 is bit-wise 'ORed' 612 with an accrued exception field 506 if a trap enable mask field 504 is configured to mask the exception, with the 'ORed' result written back in the accrued exception field 506. If the trap enable mask field 504 is configured to enable the exception, the accrued exception field 506 and a current exception field 508 are cleared, and an unfinished floating-point exception flag is set in a floating-point trap type field 502. The actual sub-instruction(s) causing the exception is determined through software.

Exception handling for simd floating point-instructions

A CPU adapted to calculate a checksum simultaneously on multiple values packed into a single register. An adder is provided which adds a number of values packed into a first register to a number of packed values from a second register. The adder is constructed, or partitioned, so that the values do not propagate their carry bit to the next value. A special carry bit adder is provided which will add a carry bit out of each partitioned portion back into the sum value to generate the sum required by the checksum protocol.

SIMD TCP/UDP checksumming in a CPU

Certain bits in existing op code formats for a processor do not change from one instruction to another when particular classes of instructions are used. Applicants optionally utilize one or more of these bits to identify one of a plurality of different register files from which to retrieve operands or to store the results of an operation. These bits along with allocated address bits in predetermined address fields now allow the processor to address many more registers. This can be used to increase the performance of the processor. Those programs not utilizing the bits outside of the address fields for designating a particular register file are backwards compatible with the modified processor.

Auxiliary register file accessing technique

PROBLEM TO BE SOLVED: To increase the throughput of a quotient digit without increasing cycle time SOLUTION: The implementation of a base 8 peforms a continuous connection for three partial remainder arithmetic circuit and overlaps three quotient selection circuits(QSLC) 302 to 304 Two carry holding adders 307 estimatingly operate result partial remainders which are found corresponding to each value of -1, 0, +1 of the quotient digit by adding a divisor and the complement of 2 Thus, the critical path composed of an SRT repetition generating a quotient digit becomes shorter

J. Arjun Prabhu

Papers

Exception handling for simd floating point-instructions

SIMD TCP/UDP checksumming in a CPU

Auxiliary register file accessing technique

Circuit for computing/dividing of square root of radical number 2 by three overlapped stages with presumptive computing