This paper examines the effect of technology scaling and microarchitectural trends on the rate of soft errors in CMOS memory and logic circuits. We describe and validate an end-to-end model that enables us to compute the soft error rates (SER) for existing and future microprocessor-style designs. The model captures the effects of two important masking phenomena, electrical masking and latching-window masking, which inhibit soft errors in combinational logic. We quantify the SER due to high-energy neutrons in SRAM cells, latches, and logic circuits for feature sizes from 600 nm to 50 nm and clock periods from 16 to 6 fan-out-of-4 inverter delays. Our model predicts that the SER per chip of logic circuits will increase nine orders of magnitude from 1992 to 2011 and at that point will be comparable to the SER per chip of unprotected memory elements. Our result emphasizes that computer system designers must address the risks of soft errors in logic circuits for future designs.

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Modeling the effect of technology trends on the soft error rate of combinational logic

Physical mechanisms responsible for nondestructive single-event effects in digital microelectronics are reviewed, concentrating on silicon MOS devices and integrated circuits. A brief historical overview of single-event effects in space and terrestrial systems is given, and upset mechanisms in dynamic random access memories, static random access memories, and combinational logic are detailed. Techniques for mitigating single-event upset are described, as well as methods for predicting device and circuit single-event response using computer simulations. The impact of technology trends on single-event susceptibility and future areas of concern are explored.

Basic mechanisms and modeling of single-event upset in digital microelectronics

Electronic devices in space environments can contain numerous types of oxides and insulators. Ionizing radiation can induce significant charge buildup in these oxides and insulators leading to device degradation and failure. Electrons and protons in space can lead to radiation-induced total-dose effects. The two primary types of radiation-induced charge are oxide-trapped charge and interface-trap charge. These charges can cause large radiation-induced threshold voltage shifts and increases in leakage currents. Two alternate dielectrics that have been investigated for replacing silicon dioxide are hafnium oxides and reoxidized nitrided oxides (RNO). For advanced technologies, which may employ alternate dielectrics, radiation-induced voltage shifts in these insulators may be negligible. Radiation-induced charge buildup in parasitic field oxides and in SOI buried oxides can also lead to device degradation and failure. Indeed, for advanced commercial technologies, the total-dose hardness of ICs is normally dominated by radiation-induced charge buildup in either parasitic field oxides and/or SOI buried oxides. Heavy ions in space can also degrade the oxides in electronic devices through several different mechanisms including single-event gate rupture, reduction in device lifetime, and large voltage shifts in power MOSFETs.

Radiation Effects in MOS Oxides

We investigated scaling of the atmospheric neutron soft error rate (SER) which affects reliability of CMOS circuits at ground level and airplane flight altitudes. We considered CMOS circuits manufactured in a bulk process with a lightly-doped p-type wafer. One method, based on the empirical model, predicts a linear decrease of SER per bit with decreasing feature size L/sub G/. A different method, based on the MBGR model, predicts even faster decrease of SER per bit than linear. If the increasing number of bits is taken into account, then the SER per chip is not expected to increase faster than linearly with decreasing L/sub G/.

Impact of CMOS technology scaling on the atmospheric neutron soft error rate

Radiation-induced single event upsets (SEUs) pose a major challenge for the design of memories and logic circuits in high-performance microprocessors in technologies beyond 90nm. Historically, we have considered power-performance-area trade offs. There is a need to include the soft error rate (SER) as another design parameter. In this paper, we present radiation particle interactions with silicon, charge collection effects, soft errors, and their effect on VLSI circuits. We also discuss the impact of SEUs on system reliability. We describe an accelerated measurement of SERs using a high-intensity neutron beam, the characterization of SERs in sequential logic cells, and technology scaling trends. Finally, some directions for future research are given.

Characterization of soft errors caused by single event upsets in CMOS processes

The results are reported for a comprehensive analytical and experimental study of galactic cosmic-ray-induced errors in MOS devices. An error rate model is described which utilizes exact expressions for a path-length distribution function and a Linear Energy Transfer (LET) spectrum for the cosmic ray environment to calculate the expected cosmic-ray-induced error rate in space for a given parallel-piped-shaped sensitive volume. The model validity is confirmed by comparison of predictions to bit-error data from devices in orbiting satellites, and to cosmic ray simulation measurements on the same device types at a cyclotron. The experimental results and model predictions are described for a wide variety of device types, including NMOS, PMOS, CMOS/bulk, CMOS/SOS, and ANOS.

Cosmic-Ray-Induced Errors in MOS Devices

The methodology and results are presented for a detailed analysis to predict the galactic cosmic ray induced bit-error rate in three commercially availale CMOS RAM types. A summary of cyclotron simulation data is provided and utilization of the experimental results in the Cosmic Ray Induced Error Rate (CRIER) model is described.

CMOS RAM Cosmic-Ray-Induced-Error-Rate Analysis

As device feature size is scaled down for Very Large Scale Integration (VLSI) and Very High Speed Integrated Circuit (VHSIC) applications, consideration must be given to potential increased vulnerabiliity to single particle induced upset (memory soft error or processor logic error) from the natural radiation environment. This paper describes a detailed computer aided modeling study to predict the effect of scaling on the single event upset rate in CMOS memory cells in the galactic cosmic ray environment typical of high altitude satellite orbits.

Effect of CMOS Miniaturization on Cosmic-Ray-Induced Error Rate

New test data from the Jet Propulsion Laboratory (JPL), The Aerospace Corporation, Rockwell International (Anaheim) and IRT have been combined with published data of JPL [1,2] and Aerospace [3] to form a nearly comprehensive body of single event upset (SEU) test data for heavy ion irradiations. This data has been arranged to exhibit the SEU susceptibility of devices by function, technology and manufacturer. Clear trends emerge which should be useful in predicting future device performance.

Trends in Parts Susceptibility to Single Event Upset from Heavy Ions

Heavy-ion-induced permanent damage in MNOS gate insulators has been investigated using a Cf252 fission source. The electric field and ion LET thresholds for onset of the damage has been characterized. The results are consistent with a thermal runaway mechanism in the silicon nitride layer initiated by a single heavy ion and leading to a permanent high conductivity path through the dielectric layers.

J. C. Pickel

Papers

Cosmic-Ray-Induced Errors in MOS Devices

CMOS RAM Cosmic-Ray-Induced-Error-Rate Analysis

Effect of CMOS Miniaturization on Cosmic-Ray-Induced Error Rate

Trends in Parts Susceptibility to Single Event Upset from Heavy Ions

Heavy Ion Induced Permanent Damage in MNOS Gate Insulators