Методы подавления шумов и помех в электронных системах. (Noise reduction techniques in electronic systems)

As circuit boards are increasingly required to transmit signals at higher and higher speeds, signal and power integrity become increasingly crucial. Rules of thumb that you have used over and over again to prevent signal loss no longer apply to these new, high-speed, high-density circuit designs. This leading-edge circuit design resource offers you the knowledge needed to quickly pinpoint transmission problems that can compromise your entire circuit design. Discussing both design and debug issues at gigabit per second data rates, the book serves as a practical reference for your projects involving high-speed serial signaling on printed wiring boards. Step-by-step, this book goes from reviewing the essentials of linear circuit theory, to examining practical issues of pulse propagation along lossless and lossy transmission lines. It provides detailed guidelines for crosstalk, attenuation, power supply decoupling, and layer stackup tradeoffs (including pad/antipad tradeoffs). Other key topics include the construction of etched conductors, analysis of return paths and split planes, microstrip and stripline characteristics, and SMT capacitors. Filled with on-the-job-proven examples, this hands-on reference is the book that you can turn to time and again to design out and troubleshoot circuit signal loss and impedance problems.

High-speed circuit board signal integrity

Aluminium electrolytic capacitors (AECs) are used in dc-link of single-phase grid connected solar photovoltaic (PV) inverters to suppress the dc-link voltage oscillation. With aging its capacitance decreases and equivalent series resistance (ESR) increases, which may lead to increase in voltage ripple, thereby reducing average power extracted from solar PV and/or damage the semiconductor switches due to overvoltage. Further, prolonged use of the aged capacitor could lead to the open circuit of the dc-link due to vaporization of the electrolyte. Therefore, to enhance the reliability of the system by predictive maintenance, it is necessary to monitor the health of AEC. A quasi-online method for condition monitoring of the AECs in solar inverters is proposed in this paper. This method is active during the night when there is no solar irradiance. In this case, the current of various odd harmonic frequencies are injected by the inverter and dc-link capacitor impedances at various frequencies are evaluated. Using these impedance values, least mean square algorithm is used to estimate the ESR and capacitance values. The magnitude of each injected harmonic current is kept within the limits prescribed by IEEE 929-2000 standard. The key advantage of the technique is that it combines the estimation of both ESR and capacitance to determine the health. Further, it does not require significant processing capability and is implemented in the existing digital processor/controller used for inverter control. Detailed simulation studies are carried out using MATLAB-Simulink. Proposed scheme is verified experimentally on a scaled down version of a grid connected solar inverter. Puncturing based technique is used for accelerated aging of the capacitor. Estimated values of ESR and C are in agreement to that measured from LCR meter.

Quasi-Online Technique for Health Monitoring of Capacitor in Single-Phase Solar Inverter

Challenges for measurements of high-frequency passive components for power electronics applications include the difficulty in measuring the small real impedance of an efficient component, the need for high-level excitation to match operating conditions for a nonlinear component, and in some applications, the need to measure very low impedances. Commercial impedance analyzers are tested and shown to be able to meet some of these requirements. To extend their capabilities, a new test fixture with less than 100 pH stray inductance has been developed for measurements of low impedances. The use of a power booster to extend drive capability to higher powers is also presented.

/pdf/impedance-analyzer-measurements-of-high-frequency-power-4vyfv8sglx.pdf

Impedance-analyzer measurements of high-frequency power passives: techniques for high power and low impedance

This paper presents an overview of the electrical analysis and electrical design processes and techniques used to develop package-level interconnect technologies to meet Intel’s present and future performance challenges. The three areas of focus in electrical design of package interconnects: signal integrity, power delivery, and electromagnetic compatibility are discussed. Details of technology development and design choices made to meet the electrical performance requirements of some of Intel’s most recent products are discussed. Some of the specific topics discussed include design and analysis flows, design techniques for impedance control and improved signal integrity, power decoupling solutions, voltage regulation module (VRM) analysis, and design for EMI control and improvement. Design and technology trade offs to meet the varied cost goals for different product lines resulting from Intel’s recent market segmentation are also discussed using examples such as Intel’s high-end server product line, Itanium processors, and Intel’s value-PC line, Celeron processors. The importance of die-to-motherboard design integration early in the technology development cycle is also highlighted as critical in optimizing design for performance and cost.

http://mprc.pku.edu.cn/~liuxianhua/chn/corpus/Notes/articles/itj/source/2000q3_03interconnect.pdf

Package-Level Interconnect Design for Optimum Electrical Performance

To improve the accuracy for high frequency characterization of capacitors with very low inductance values, a technique is developed. The first part of the technique requires a standard calibration for a network analyzer. Then s-parameter measurements for test fixtures and adapters are measured. A high frequency circuit model for every connector or test fixture from the calibrated port to the device under test (DUT) is then de-embedded one at a time, using the measured data as a reference and each time adding in the previously de-embedded circuit model. The difference between the measured data and the simulated data is forced to be less than 1%. This stringent requirement is necessary for obtaining the high accuracy equivalent series inductance (ESL) and resistance (ESR). The requirement also guarantees the accuracy of high frequency parasitic capacitance and resistance of a capacitor. After the high frequency circuit models for all test fixtures and adapters are found, s-parameter measurements for a capacitor mounted on a test fixture with an adapter are measured. When the circuit models for the test fixture and adapter are put together and the whole system is matched to the measured s-parameter data for the whole system, the circuit model of a capacitor has been found. In this paper, two new capacitor models and several discontinuity models are also reported. The new capacitor models are valid for the entire frequency range. The discontinuity models are fully consistent with the real physical structure of test fixtures. Different capacitors from various suppliers are characterized and the high frequency circuit models are also provided.

J. Canner

Papers

A new technique for high frequency characterization of capacitors