Designing a new microprocessor is extremely time-consuming.One of the contributing reasons is that computerdesigners rely heavily on detailed architectural simulations,which are very time-consuming. Recent workhas focused on statistical simulation to address this issue.The basic idea of statistical simulation is to measurecharacteristics during program execution, generate asynthetic trace with those characteristics and then simulatethe synthetic trace. The statistically generated synthetictrace is orders of magnitude smaller than the original programsequence and hence results in significantly fastersimulation.This paper makes the following contributions to the statisticalsimulation methodology. First, we propose the useof a statistical flow graph to characterize the control flow ofa program execution. Second, we model delayed update ofbranch predictors while profiling program execution characteristics.Experimental results show that statistical simulationusing this improved control flow modeling attainssignificantly better accuracy than the previously proposedHLS system. We evaluate both the absolute and the relativeaccuracy of our approach for power/performance modelingof superscalar microarchitectures. The results showthat our statistical simulation framework can be used to efficientlyexplore processor design spaces.

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Control Flow Modeling in Statistical Simulation for Accurate and Efficient Processor Design Studies

Statistical simulation enables quick and accurate design decisions in the early stages of computer design, at the processor and system levels. it complements detailed but slower architectural simulations, reducing total design time and cost.

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Statistical simulation: adding efficiency to the computer designer's toolbox

Performance evaluation is at the foundation of computer architecture research and development Contemporary microprocessors are so complex that architects cannot design systems based on intuition and simple models only Adequate performance evaluation methods are absolutely crucial to steer the research and development process in the right direction However, rigorous performance evaluation is non-trivial as there are multiple aspects to performance evaluation, such as picking workloads, selecting an appropriate modeling or simulation approach, running the model and interpreting the results using meaningful metrics Each of these aspects is equally important and a performance evaluation method that lacks rigor in any of these crucial aspects may lead to inaccurate performance data and may drive research and development in a wrong direction The goal of this book is to present an overview of the current state-of-the-art in computer architecture performance evaluation, with a special emphasis on methods for exploring processor architectures The book focuses on fundamental concepts and ideas for obtaining accurate performance data The book covers various topics in performance evaluation, ranging from performance metrics, to workload selection, to various modeling approaches including mechanistic and empirical modeling And because simulation is by far the most prevalent modeling technique, more than half the book's content is devoted to simulation The book provides an overview of the simulation techniques in the computer designer's toolbox, followed by various simulation acceleration techniques including sampled simulation, statistical simulation, parallel simulation and hardware-accelerated simulation

Computer Architecture Performance Evaluation Methods

Microprocessor simulators are very popular in research and teaching environments. For example, functional simulators are often used to perform architectural studies, to fast-forward over uninteresting code, to generate program traces, and to warm up tables before switching to a more detailed but slower simulator. Unfortunately, most portable functional simulators are on the order of 100 times slower than native execution. This paper describes a set of novel techniques and optimizations to synthesize portable functional simulators that are only 6.6 times slower on average (16 times in the worst case) than native execution and 19 times faster than SimpleScalar's sim-fast on the SPECcpu2000 programs. When simulating a memory hierarchy, the synthesized code is 2.6 times faster than the equivalent ATOM code. Our fully automated synthesis approach works without access to source/assembly code or debug information. It generates C code, integrates optional user-provided code, performs unwanted-code removal, preserves basic blocks, generates low-overhead profiles, employs a simple heuristic to determine potential jump targets, only compiles important instructions, and utilizes mixed-mode execution, i.e., it interleaves compiled and interpreted simulation to maximize performance.

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Automatic Synthesis of High-Speed Processor Simulators

A method for developing an integrated circuit chip design includes the steps of developing an architecture specification defining the functions of the chip, developing a microarchitecture specification based on the architecture specification, developing a functional and structural model of the chip based on the microarchitecture specification, designing software tools for use with the chip based on the architecture specification, and designing chip verification tools based on the microarchitecture specification. The activities associated with chip development are divided into phases which may be performed concurrently. The result of the development is an RTL model of the chip which can be utilized in implementation of products without comprising proprietary circuit, layout and fabrication process information of the entity that is implementing the products.

Methods for developing an integrated circuit chip design

Microprocessor designers use multiple simulation tools with varying degrees of modeling details ranging from the instruction set of the microprocessor to the circuit implementation. We focus on tool design for the development of microarchitectures, which implement the instruction set. Microarchitecture design involves both functional and performance simulators. A functional simulator models a machine's architecture, or instruction set, with functional correctness. A performance simulator models the machine organization, or microarchitecture, and is concerned with machine performance. Sometimes these performance simulators are also referred to as cycle-accurate simulators to reflect their concern with timing issues. The FMW PowerPC-based simulation tool will help designers accurately evaluate the effectiveness and validate the correctness of new microprocessor mechanisms.

J. Combs

Papers

An integrated functional performance simulator