When using a method for processing signals in a protection system operations being complementary to each other are executed on the signals, whereby it depends on the results thereof whether the operations can be continued. Besides logic operations on input variables also complementary operations are executed in the device for carrying out the method, by means which are controlled by state machines. As a result of this a house of cards-like construction is obtained, wherein a desired switching-off takes place in case one link is missing. The device has thus become inherently safe.

A method and a device for processing signals in a protection system

A memory comprises memory cells arranged in a memory array, and an address decoder to apply memory cells selection signals to the memory array according to a read address applied to the memory. The memory comprises an address reconstruction circuit which reconstructs at least one part of the read address from the memory cells selection signals, and supplies a first reconstructed address able to detect an error injection affecting the selection signals. Particularly but not exclusively applicable to the integrated circuits for chip cards.

Memory protected against attacks by error injection in memory cells selection signals

The method involves applying a memory cell selection signal to a memory area by an address decoder according to a reading address of the data applied to a memory. A part of the reading address is reconstructed by an address reconstruction circuit to obtain a reconstructed address. A bit of the latter address is reconstructed by a polarization transistor and by applying the signal on a control terminal of the transistor, where the transistor is arranged to polarize an output node to a logic state. An error signal is activated if the reconstructed address is different from the reading address. An independent claim is also included for a memory comprising a cell memory arranged in a memory area.

Memory protected against error injection attacks on memory cell selecting signals

The coders/decoders are connected to optical numerical display units At least two coders/decoders with the same operational behavior are connected before the data delivery units Their inputs are connected to the data source A switching system switches the coders/decoders alternately in their operative and non-operative states Coders/decoders are followed by signalling devices which deliver an output signal when the coder/decoder output signals in consecutive connection phases do not coincide The above signalling devices are connected to coders/decoders through switching means which deliver at their outputs an output potential only when ac signals are applied to their inputs The signalling devices are optical display devices

Coder/decoder testing and monitoring device - signals converted from data sources into signals suitable for data transmission

A detector to detect two identical addresses during the same cycle in a TDM switching system has a one-bit location added to each different address word storing row of a control memory. Each address word sent by a cyclically operating addressing memory to a speech signal memory is also sent to the control memory and a logic 1 is written into the corresponding one-bit location. The logic 1 appears only at write time. At all other times a logic 0 appears in the one-bit location. This writing operation is preceded by a reading operation of the addressed row. Each row is read one time per cycle so that logic 1 is only read if there are two or more writing operations in the same row during a cycle.

Wrong addressing detector

A system for checking the decoding of an address previously encoded in the form of a group of N bits called input bits. The system performs, on one hand, a re-encoding of such address in the form of N output bits identical to the N input bits, and in the form of their complementary bits N, and, on the other hand, compares the identity and/or complementarity of the input and output bits. The system comprises a first arrangement of 2N relays each having a single contact, a group of n diodes (D1, D2, etc.) per contact, a group of n re-encoding matrices (M1, M2 etc.), a second arrangement of 2N relays each having a contact, and means for comparing the identity and/or the complementarity of the input and output bits.

J Darmon

Papers

System for monitoring the decoding of an address

Dispositif de controle du decodage d'une adresse

Vorrichtung zur Kontrolle der Dekodierung einer Adresse