In this paper, we present a fast fault simulator, FSIM, for combinational circuits. FSIM is based on the parallel pattern single fault propagation (PPSFP) technique. The essential idea of FSIM is to simulate the circuit in the forward levelized order and to prune off unnecessary gates in the early stages. In this way, FSIM performs fault simulations only for the gates which are affected by 'the injected faults. Another key feature employed in FSIM is the use of multiple last-in first-out (L,IFO) stacks instead of the commonly used priority queue [9]. The propagation time of the mult,iple LIFO stacks is O(n) and that of the priority queue O(n log n), where n is the number of gates in the propagation zone of the fault under consideration. The two features achieve a substantial reduction of the processing time. Experimental results for ten benchmark circuits show that FSIM outperforms other competing PPSFP fault simulators, Moreover, the efficiency of FSIM is less dependent on the circuit structure than other fault simulators. Experimental results of FSIM for various packet sizes, i.e., the number of test patterns simulated at a time, are also presented.

An efficient, forward fault simulation algorithm based on the parallel pattern single fault propagat

An extension to the Fiduccia and Mattheyses minicut algorithm (1982) allows cells to be replicated in both sides of the partition. This technique can substantially reduce the number of cut nets in a partitioned network below what can be obtained without replication. The extensions to the algorithm to permit replication are easily implemented and maintain the linear-time complexity of the algorithm. This technique is dependent solely upon the interconnect topology and the direction of signal flows between cells and nets. The formulation of cell gains is extended to model the effect of cell replication, and the necessary modifications to the algorithm are described. >

A cell-replicating approach to minicut-based circuit partitioning

The authors describe PARIS, a parallel-pattern fault simulator for synchronous sequential circuits. PARIS is based on the well-known approach of parallel pattern single fault propagation for combinational circuits and features several new techniques. Every single pattern packet is simulated by an iterative, event-driven method. Heuristic look-ahead of signal values minimizes the number of events that must be tracked. Clever circuit partitioning prevents multiple evaluation of the feedback free parts of the circuit, thus reducing the required simulation effort. Experiments show that PARIS runs at a substantially higher asymptotic speed compared with a state-of-the-art fault simulator for synchronous sequential circuits. >

PARIS: a parallel pattern fault simulator for synchronous sequential circuits

Automatic Test Pattern Generation (ATPG) systems are tools for generating tests for digital circuits Due to the complexity of very large scale integrated circuits, such systems are essential for achieving tests with high fault coverage This thesis presents time efficient ATPG systems for combinational and sequential circuits
First, a fast, effective deterministic test generation algorithm provides a time efficient ATPG system for combinational circuits This algorithm utilizes a new fast fault simulation algorithm, Parallel Pattern Critical Path Tracing (PPCPT) At the earlier stages of test set simulation, PPCPT takes advantage of critical path tracing, then dynamically transforms to parallel pattern single fault propagation as the simulation progresses
Further, for concurrent engineering design environments, an incremental ATPG concept is introduced When there is a small circuit modification, incremental test generation utilizes information from tests for the original circuit to speed up test generation for the new circuit Four incremental techniques are developed to utilize information from the original tests These four techniques and a fast deterministic test generation algorithm are combined to give ICAT (Incremental Combinational ATPG) ICAT speeds up ATPG by up to a factor of fifteen
In sequential test generation, a fast, efficient deterministic test generation algorithm, called Sequential ATPG (SAT), is developed SAT employs two complementary procedures: a new improved forward procedure and a simplified backward procedure Each procedure compensates for the disadvantages of the other Benchmark results show SAT is a fast algorithm and produces high fault coverage with a reasonable number of test vectors More important, SAT is a consistent algorithm that can handle difficult circuits not handled well by other algorithms as well as easy circuits
Finally, the incremental concept is extended to sequential test generation, and ISAT (Incremental Sequential ATPG) is developed In ISAT, to take advantage of information from the original tests by the backward method, the order of application of the forward and backward procedures is reversed Benchmark results indicate that ISAT improves test generation time for many cases

Time-efficient automatic test pattern generation systems

Efficient strategies to perform selectively fault-free simulation, critical path tracing in fanout-free regions, and fault simulation of stem faults in a parallel pattern evaluation environment are presented and analyzed in an implementation-independent manner. The dynamic changes in the complexity of the fault simulation components as the fault simulation progresses and faults are detected are shown to be extremely significant. In particular, fault-free simulation tends quickly to become more expensive than both the critical path tracing within fanout-free regions and the explicit simulation of stem faults. In addition, the presence of redundant faults is shown to have an inhibiting effect on the reduction of the fault simulation complexity. >

The dynamic reduction of fault simulation

It is shown how the test-detect principle can be adapted to the parallel-patterns technique for combinational fault simulation. Several techniques for implementing a parallel-test-detect simulator are presented, with techniques based on nominator analysis providing the fastest fault simulation results. The dominant-test-detect approach has proved to be effective both for small sets of patterns, as might be used in automatic test pattern generation, and for larger pattern sets that might be used in built-in self-test. >

J. Ferguson

Papers

The parallel-test-detect fault simulation algorithm