Reference NANOLAB-CONF-2002-002View record in Web of Science Record created on 2007-10-10, modified on 2017-05-10

Modelling and analysis of power dissipation in Single Electron logic

The design of three-valued schematics utilizing graphene nanoribbon field effect transistors (GNRFETs) is presented in this paper. Three-valued logic have various benefits over the conventional binary logic such as reduced area, reduced wire complexity, fast-arithmetic and logic operation and large bandwidth. In this work, the standard three-valued inverter (STI), NAND and half subtractor are presented. The proposed schematics are developed using HSPICE for validation. The performances in terms of delay, power and circuit area for GNRFET designs are also evaluated and compared with CNTFET designs. The GNRFET designs show high performance on an average up to 53.2% compared to CNTFET based designs. 

Design of Three-valued Logic Half-Subtractor using GNRFET

The design of three-valued schematics utilizing graphene nanoribbon field effect transistors (GNRFETs) is presented in this paper. Three-valued logic have various benefits over the conventional binary logic such as reduced area, reduced wire complexity, fast-arithmetic and logic operation and large bandwidth. In this work, the standard three-valued inverter (STI), NAND and half subtractor are presented. The proposed schematics are developed using HSPICE for validation. The performances in terms of delay, power and circuit area for GNRFET designs are also evaluated and compared with CNTFET designs. The GNRFET designs show high performance on an average up to 53.2% compared to CNTFET based designs.

MVL Sequential Circuits

Succeeding the Moore's law CMOS technology accumulated extreme device complexity with larger interconnects. But owing to physical scaling limitations CMOS technology itself is degrading the overall performance of binary logic ICs. This has augmented the urgency of Multi Valued Logic (MVL). A ternary logic or a three-valued logic is contemplated as the noblest radix of all assorted MVL formulates. The synthesis of ternary future ready logic circuits is itself a benchmark in device research arena. Yet there sustain ample research dearth to realize ternary hardware to meet the common needs of basic living. To cope up with such pivotal necessitates the authors here render a heuristic approach in developing ternary gates and flip-flops. Besides, Single Electronic technology is incorporated to further enhance the novel nature of the models in this paper. Initially the Single Electron ternary gates andflip-flops are simulated using Monte Carlo based SIMON 2.0 simulator and the simulation results exhibit a simple structure with less propagation delay and lower power consumption compared to conventional CMOS topology. Further it also ratify that such models are completely trustworthy and it accord perfectly with next generation computing having the merits of higher information storing capacity and thereby minimizing interconnections. Eventually more transistors can be cramped into the reduced chip dia in order to enhance the performance of SET MVL circuits.

J. Gope

Papers

Modelling of single electron ternary flip-flop using SIMON