A Thin-Film-Silicon-On-Insulator Complementary BiCMOS (TFSOI CBiCMOS) technology has been developed for low power applications. The technology is based on a manufacturable, near-fully-depleted 0.5 /spl mu/m CMOS process with the lateral bipolar devices integrated as drop-in modules for CBiCMOS circuits. The near-fully-depleted CMOS device design minimizes sensitivity to silicon thickness variation while maintaining the benefits of SOI devices. The bipolar device structure emphasizes use of a silicided polysilicon base contact to reduce base resistance and minimize current crowding effects. A split-oxide spacer integration allows independent control of the bipolar base width and emitter contact spacing. Excellent low power performance is demonstrated through low current ECL and low voltage, low power CMOS circuits. A 70 ps ECL gate delay at a gate current of 20 /spl mu/A is achieved. This represents a factor of 3 improvement over bulk trench-isolated double-polysilicon self-aligned bipolar circuits. Similarly, CMOS gate delay shows a factor of 2 improvement over bulk silicon at a power supply voltage of 3.3 V. Finally, a 460 /spl mu/W 1 GHz prescaler circuit is demonstrated using this technology. >

TFSOI complementary BiCMOS technology for low power applications

The breakdown voltage in fully depleted SOI n-MOSFET's has been studied over a wide range of film thicknesses, channel dopings, and channel lengths. In lightly-doped films, the breakdown voltage roll-off at shorter channel lengths becomes much less severe as the film thickness is reduced. This is a result of improved resistance to punchthrough and DIBL effects in thinner SOI. Consequently, at channel lengths below about 0.8 /spl mu/m, ultrathin (50 nm) SOI can provide better breakdown voltages than thicker films. At heavier doping levels the punchthrough and DIBL are suppressed, and there is little dependence of breakdown voltage on film thickness. Two-dimensional simulations have been used to investigate the breakdown behavior in these devices. It is found that the drain-induced barrier lowering affects the breakdown voltage both directly, via punchthrough, and indirectly through its effect on the current flow and hole generation in the high-field regions. >

Detailed characterization and analysis of the breakdown voltage in fully depleted SOI n-MOSFET's

Ultrathin silicide with thickness less than 30 nm and specific contact resistivity to silicon less than mid-10/sup -7//spl Omega/-cm/sup 2/ is necessary for achieving low contact resistance in a sub-0.25-/spl mu/m fully-depleted (FD) silicon-on-insulator (SOI) CMOS technology. This contact problem becomes even more severe as one continues to scale down the device dimensions. We first studied the effects of source/drain series resistance and gate sheet resistance on the device speed performance and obtained a set of desired design criteria. These were used along with a transmission line model to yield a silicide design space, which was then used to evaluate the experimental results. Both cobalt and titanium silicide processes were implemented and found to satisfy the design criteria. Final device characteristics were also measured. Several process integration issues related to contact dielectric deposition and contact barrier integrity were found to greatly impact the final contact properties. These along with the detailed fabrication process are discussed.

Thin silicide development for fully-depleted SOI CMOS technology

A fully-depleted (FD) silicon-on-insulator (SOI) CMOSFET, whose source/drain (S/D) layers are completely silicided in depth with cobalt, have been successfully fabricated for the first time on a 20-nm-thick SOI layer using our advanced cobalt salicide technology. The fully-silicided S/D-nMOSFET and pMOSFET exhibit the same level of series resistance and significantly reduced bipolar junction transistor (BJT) action, compared to the conventional partially-silicided structure. The small series resistance is due to the small contact resistivity of CoSi/sub 2/ to both n/sup +/- and p/sup +/-diffusion layers, which are estimated to be on the order of low-10/sup -8/ /spl Omega/-cm/sup 2/ and high-10/sup -8/ /spl Omega/-cm/sup 2/, respectively. The improved BJT property is speculated to stem from the cobalt atoms diffused in the vicinity of the n/sup +//p junction, which can work as an effective lifetime killer. The fully-silicided S/D structures with CoSi/sub 2/ prove to be a valid structure for the FD SOI CMOS devices in the sub-0.13 /spl mu/m technology node.

https://ieeexplore.ieee.org/iel5/16/26455/01177997.pdf

Fully-depleted SOI CMOSFETs with the fully-silicided source/drain structure

Two manufacturable technologies of fully-depleted (FD) thin-film silicon-on-insulator (SOI) MOSFET's for low-power applications are proposed in this paper. To maintain high current drive while aggressively thinning down the SOI film, silicide is to be formed on Ge-damaged silicon layers. Ge preamorphization facilitates silicide formation at low temperature (/spl sim/450/spl deg/C) and effectively controls the silicide depth without void formation. It also reduces the floating body effect. In addition, a reliable gate work-function engineering is introduced for good threshold voltage management. A p/sup +/SiGe/Si stack gate alleviates the threshold voltage instability of SOI due to film thickness nonuniformity and broadens the design window for channel doping. These advanced technologies, compatible with existing bulk CMOS technology, are integrated into SOI CMOS process. Excellent electrical device results are presented.

Advanced technologies for optimized sub-quarter-micrometer SOI CMOS devices

As semiconductor device dimensions shrink and packing-densities rise, issues of parasitic capacitance and circuit speed become increasingly important. The use of Thin-Film Silicon-On-Insulator (TFSOI) substrates for device fabrication is being explored in order to reduce power consumption and increase performance. SIMOX (Silicon separation by Implanted OXygen) and BESOI( Bond and Etch back Silicon On Insulator) can be used for device fabrication at this time, however the subject of this study will be CMOS device structures built on SIMOX only. Fabrication of modern MOSFET's requires formation of a silicide in both the poly gate and mono-silicon Source/Drain regions. In our case the contact silicide under investigation is a TiSi/sub 2/ layer followed by Al(Cu) metal interconnect lines. TiSi/sub 2/ has a relatively low contact resistance and reduces the series resistance of both source/drain as well as gate regions. >

J. Jones

Papers

Behavior of contact-silicided TFSOI gate-structures