Disclosed is a multiprocessor computer system including a plurality of processor modules with each of the processor modules including at least one processor and a cache memory which is shared by all of the processors of each processor module. The processor modules are connected to a system bus which comprises independent data, address, vectored interrupt, and control buses. A system memory which is shared by all the processor modules is also connected to the buses, and the cache memories in each processor module store those memory locations in the main memory most frequently accessed by the processors in its module. A system control module controls the operation and interaction of all of the modules and contains the bus arbiters for the vector, data and address buses. The system control module also controls the retrying of requests which are not completed and should any requester fail to obtain access to a bus, the system control module also unjams this deadlock. Each of these multiprocessor computer systems can be connected to another multiprocessor computer system through an interface which includes a cache for housing frequently accessed locations of the other multiprocessor system.

Multiprocessor computer system employing a plurality of tightly coupled processors with interrupt vector bus

The present invention provides an improved arbitrator for use in allocating access to a common resource coupled to a plurality of data processing devices ("agents"). An arbitrator is coupled between the resource and each of the agents, for selectively enabling individual agents to access the resource in accordance with a predetermined priority hierarchy. The arbitrator, in the presently preferred embodiment, receives request signals transmitted by an agent desiring to access the resource and allocates ownership on a first come first serve basis or by a four level hierarchy in the case of simultaneous requests. The arbitrator includes a timing circuit which times predetermined periods between request signals transmitted by the agent which has acquired ownership. The arbitrator senses multiple requests for access by the agent within the predetermined time period, and, enters a lock condition if the agent issues a second request within the predefined period. The lock condition provides exclusive access to the agent which acquired ownership and transmitted the multiple request signals within the period or locks out one or more other agents. This lock condition locks out selected other agents form acquiring access until the enabled agent ceases to transmit the multiple request signals within the period. The effect of the lock is to provide continuous or enhanced resource access to those agents which transmit data faster than the other agents and in a burst fashion.

Arbitrator for allocating access to data processing resources

A system for pipelining bus requests includes a bus, at least one node coupled to the bus, and a bus coordinator coupled to the node. The node uses a single bus request signal to both request control of the bus from the bus coordinator, and to retain control of the bus. In response to an asserted bus request signal from the node, the coordinator sends an asserted bus grant signal to the node to grant the node control of the bus. This bus grant signal tracks the bus request signal so that as long as the bus request signal remains asserted, the bus grant signal also is asserted. To allow for pipelining, the bus coordinator maintains the bus grant signal in an asserted state for at least one clock cycle after the bus request is deasserted. By holding the bus grant signal in the asserted state for one extra cycle, the coordinator gives the node time to deassert and then to reassert the bus request signal before the bus grant signal changes state. If the bus request is reasserted within the extra cycle, the coordinator continues to maintain the bus grant signal in the asserted state so that no state change is experienced by the bus grant signal between the deassertion and the reassertion of the bus request signal. In this manner, consecutive bus requests are pipelined. To further increase the efficiency of the system, the node deasserts the bus request signal at least one clock cycle before it sends its last set of information, and continues to send information signals in the following clock cycle. By so doing, the node ensures that the extra clock cycle of the bus grant is not wasted.

Method and system for pipelining bus requests

A VXI device which intelligently monitors transactions on the VXI bus and begins early cycles on the bus where possible, thereby improving system performance. The VXI 0device includes a VXI bus master device and a VME bus requester. When the bus master desires the bus, the VXI bus master issues a Device Wants Bus signal to its VME requester directing the requester to gain control of the VXI bus for the device or master. The VME requester then attempts to gain control of the bus for the bus master. According to the present invention, the VME requester also monitors the VXI bus and generates the bus release signal to the master to inform the master whether it is about to lose the bus. The bus release signal provides an indication to the bus master whether the bus master can begin early cycles on the bus. Therefore, the present invention provides improved performance of VXI controllers and devices coupled to the VXI bus. This provides improved performance of instrumentation and test measurement applications, as well as other applications which use a VXI or VME-based bus.

VXIbus device which intelligently monitors bus conditions and begins early cycles for improved performance

A mechanism is provided in a microprocessor bus interface to eliminate the turnabout in those cases where the same slave is involved in consecutive read data bus tenures or where the same master and slave are involved in consecutive write data bus tenures. A new optional signal is added to the bus interface, called pre-last transfer acknowledge. The signal is asserted by the slave one cycle before the last transfer acknowledge signal is asserted. The signal is intended to be received by the system's bus arbiter. If the current data tenure and the next data tenure are both read operations directed to the same slave (such as the memory controller) or both write operations from the same master to the same slave, then the arbiter may grant the data bus to the master of the next data tenure the cycle following the assertion of the pre-last transfer acknowledge indicator. This allows the arbiter to grant the bus a cycle earlier than it normally could (where it would have to see the final transfer acknowledge signal before it could grant the bus). Thus, the bus turnaround cycle is eliminated and data bus bandwidth is increased by up to twenty percent.

Method to improve bus latency and to allow burst transfers of unknown length

This invention is a method for decreasing the arbitration overhead required to transfer messages on a shared multiprocessor bus.

J.L. Coale

Papers

Method for decreasing arbitration overhead