Three parallel algorithms for logic simulation have been developed and implemented on a general-purpose shared-memory parallel machine. The first algorithm is a synchronous version of a traditional event-driven algorithm which achieves speedups of 6 to 9 with 15 processors. The second algorithm is a synchronous unit-delay compiled-mode algorithm which achieves speedups of 10 to 13 with 15 processors. The third algorithm is totally asynchronous with no synchronization locks or barriers between processors and the problems of massive state storage and deadlock that are traditionally associated with asynchronous simulation have been eliminated. The processors work independently at their own speed on different elements and at different times. When simulating circuits with little or no feedback, the asynchronous simulation technique varies between speeds one to three times faster than the conventional event-driven algorithm using one processor and depending on the circuit, achieves 10 to 20% better utilization using 15 processors. >

Parallel logic simulation on general purpose machines

This paper presents a methodology for empirically determining the amount of parallelism on a CMOS VLSI chip. Six chips are measured, and the effect of input choice and circuit size is studied. The unexpectedly low parallelism measured here suggests that certain strategies for parallel simulators may be doomed, and earlier efforts to extrapolate parallelism from small circuits to large circuits may have been overly optimistic.

An empirical study of on-chip parallelism

A model for studying the effects of timing models and synchronization strategies for event-driven parallel logic-level simulation is presented. Two timing models, variable-delay and unit-delay, and two synchronization strategies, synchronous and conservative asynchronous, are discussed. The average parallelism of circuits using the two timing models are compared, and the execution times of circuits using various timing models and synchronization strategies are considered. It is shown that the circuit parallelism using unit-delay timing provides an upper bound on that of any timebase used in variable-delay timing and that with either timing model, the execution time of the conservative asynchronous strategy is a lower bound over the synchronous strategy, assuming an unlimited number of processors. However, assuming that all events take the same amount of time, it is shown that with unit-delay timing, the execution time of the synchronous strategy equals that of the asynchronous strategy. >

A time-based model for investigating parallel logic-level simulation

The optimal level of performance from parallel discrete-event simulation depends on the circuit being simulated, the vectors being simulated, and the machine on which the simulation is being performed. Empirical studies based on very simple models suggest that the amount of parallelism available in typical circuits is very small. A model of optimal performance for a machine with an infinite number of processors having uniform memory accesses is presented. It demonstrates that some circuits have significantly more parallelism than previously believed. The model is refined to define the optimal load partitioning for a machine with a finite number of processors with uniform access and extended to define the optimal static data partitioning. A metric is obtained which can be used to benchmark different models of parallel simulation. The effectiveness of these models in detecting performance problems of the version of RSIM running on the BBN Butterfly is shown. >

Taking advantage of optimal on-chip parallelism for parallel discrete-event simulation

Logic simulation is a critical step in the design of a logic circuit. With the growing complexity of designs today, a large number of test vectors needs to be applied to the circuit to determine if the circuit behaves logically as it is supposed to. Not surprisingly, then, simulation is one of the major bottlenecks in the design process. Significant advances have been made in both software and hardware simulation. We survey some of the recent advances, with an emphasis on their main ideas.

Some recent advances in software and hardware logic simulation

Integrated circuit technology has been advancing at a phenomenal rate over the last several years, and promises to continue to do so. If circuit design is to keep pace with fabrication technology, radically new approaches to computer-aided design will be necessary. One appealing approach is general purpose parallel processing. This thesis explores the issues involved in developing a framework for circuit simulation which exploits the locality exhibited by circuit operation to achieve a high degree of parallelism. This framework maps the topology of the circuit onto the multiprocessor, assigning the simulation of individual partitions to separate processors. A new form of synchronization is developed, based upon a history maintenance and roll back strategy. The circuit simulator PRISM was designed and implemented to determine the efficacy of this approach. The results of several preliminary experiments are reported, along with an analysis of the behavior of PRISM.

J. M. Aronld

Papers

Parallel simulation of digital lsi circuits