A CMOS process incorporates self-aligned buried contacts, lightly doped source/drain structures, and sidewall oxide spacers. The process is tailored so that individual process steps and structural features serve several functions, thereby providing the desirable structural features and small geometry in conjunction with fast operational speeds, reduced Miller capacitance and short channel effects in a process of minimum complexity.

Totally self-aligned CMOS process

It is found that average interconnection lengths in a very large scale integrated (VLSI) circuit that is functionally partitioned do not continue to increase as device sizes are scaled down and chips become more densely packed. Although pin requirements still increase, this increase is much smaller than expected from common expressions of Rent's rule. These results suggest that the important dimension in VLSI is of information flow.

Interconnection lengths and VLSI

Some of the trends in integrated circuit process development are described. The motivations or technical reasons for this activity are discussed. This effort will continue to develop the downsizing that increases functional density and performance. Limiting factors are examined and new technical developments that could enable CMOS density to be comparable with NMOS density are explored. Various isolation techniques are described and the influence on performance of well profiles and doping concentrations are examined. These trends have a beating on the choice of gate electrode materials. Reliability factors governing the gate dielectric thickness are discussed briefly. MOSFET diode capacitance is shown to be the predominant limiting factor at the device level. Methodologies that could be used to reduce device parasitics are considered in detail. Device scaling below 1-µm calls for changes in contact metallization techniques. Trends in metallization technology and the various methods of fabricating multilevel interconnections when the via sizes become very small are described. The processing methods being investigated to overcome device limitations are examined and compared. In some cases, the present technical difficulties of these methods are discussed. The general conclusion of this work is that "downsizing" will continue, but advances will be more dependent upon innovative processes and device research, whereas in the past, scaling rules were adequate and progress was evolutionary.

Trends in advanced process technology&#8212;Submicrometer CMOS device design and process requirements

A novel multilevel metallization scheme has been developed that uses tungsten for the primary level of interconnection. Grooves that are 1- mu m wide and 2.0- mu m deep, corresponding to a level of line conductor interconnection, are pattern-etched into a planar layer of oxide dielectric. They are filled by isotropically depositing a blanket layer of pure tungsten using low-pressure chemical vapor deposition (CVD), followed by etch-back of the tungsten to produce a filled-interconnection-groove (FIG) conductor structure. Fabricated FIG conductors display an average sheet resistivity of 48 m Omega /square, comparable to conventional aluminum conductors. In addition, FIG metallization provides excellent planarity and greatly improved electromigration strength, and it facilitates the use of stacked vias. >

High-density high-reliability tungsten interconnection by filled interconnect groove metallization

A new device interconnect scheme for sub-micron VLSI has been developed. In this technology N+ and P+ diffusions and N+ and P+ gates of a CMOS process can be directly connected in any combination desired without the use of contacts or aluminum. This provides much improved packing density over conventional processes. Since the source/drain (S/D) contacts can extend over the field oxide regions, minimum sized S/D diffusion areas can be used. This leads to a significant decrease in parasitic diffusion capacitances relative to other processes. Several devices can share one contact when they need to communicate, and so the total number of contacts can be greatly reduced. Since the contacts do not have to be limited to minimum dimensions a relaxation of sub-micron contact processing is achieved. In addition the use of a self-aligned silicide reduces interconnect and other device parasitic resistances. NMOS and PMOS devices have been successfully fabricated using this process.

http://ieeexplore.ieee.org/iel5/9950/31922/01484428.pdf

A new device interconnect scheme for sub-micron VLSI

An overview is given of a silicon-gate NMOS fabrication process used to realize a 450000 transistor, 32-bit single-chip CPU that operates at a worst case 18 MHz clock frequency The technology utilizes 15-/spl mu/m lines and 10-/spl mu/m spaces on all critical levels, and provides tungsten dual layer metallization The device and interconnect structure for this 8-mask process is outlined as a sequence through the process flow Linewidth and alignment statistics are given for the optical reduction-projection step-and-repeat lithography used in this technology

J.M. Mikkelson

Papers

An nMOS VLSI process for fabrication of a 32-bit CPU chip