ESD Phenomena and Test Methods The Physics of ESD Protection Circuit Elements Requirements and Synthesis of ESD Protection Circuits Design and Layout Requirements Analysis and Case Studies Modelling of ESD in Integrated Circuits Effects of Processing and Packaging.

ESD in silicon integrated circuits

A memory cell array has a first and a second storage area. The first storage area has a memory elements selected by an address signal. The second storage area has a memory elements selected by a control signal. A control circuit has a fuse element. When the fuse element has been blown, the control circuit inhibits at least one of writing and erasing from being done on the second storage area.

Nonvolatile Semiconductor Memory Device

A circuit-level simulator for ESD and EOS is presented. Equations for modeling the high current behavior of NMOS and PMOS transistors have been developed and implemented in SPICE. A simple and practical extraction methodology for obtaining the bipolar parameters is given, which uses the three terminal currents obtained from a single high current I-V curve. Simulation results are presented and compared to experimental data for single devices as well as a practical output circuit.

Modeling MOS snapback and parasitic bipolar action for circuit-level ESD and high current simulations

A technique is presented to determine the effective process and design-related parameters from the high-current I-Vcharacteristics of NMOSTs, for use in the development of electrostatic discharge (ESD) protection circuits. Test structures from a fully salicided, LDD MOS process were characterized with a transmission line pulse generator to obtain the snapback voltages and the second-breakdown trigger currents (I/sub t2/) Good correlations are shown between I/sub t2/ and the human body model (HBM) ESD damage thresholds. It was seen that homogeneous current injection in the avalanching diffusions is imperative for good second breakdown behavior. A simplified thermal model, with second breakdown as the boundary condition for damage, was used in the extraction of the effective junction depth, depletion width, and transistor width under high-current conditions. Experimental data obtained for the power-to-failure as a function of the time-to-failure showed a good fit to the model. A possible extension of the technique for the use of DC characterization to monitor ESD behavior is presented. >

Characterization and modeling of second breakdown in NMOST's for the extraction of ESD-related process and design parameters

Analysis of 90 nm CMOS SET response quantifies the interaction between charge collection and charge redistribution in a matched-current-drive inverter chain. It is shown that the SET pulse width difference between an n-hit and p-hit is due to parasitic bipolar amplification on the PMOS device. This difference is exploited to optimize transistor sizing and n-well contact layout for SET RHBD in combinational logic.

Design Techniques to Reduce SET Pulse Widths in Deep-Submicron Combinational Logic

In this paper a new breakdown mechanism in a short channel MOS transistor is proposed based on experimental measurements of substrate currents. We have observed a negative resistance in the substrate current followed by conductivity modulation, similar to the operation of a unijunction transistor during switching. By adding an external substrate resistance, saturation of the substrate current was observed in conjunction with the turn-on of the parasitic NPN (source-substrate-drain) bi-polar transistor. Breakdown of the device will occur when the drain bias reaches BV CEO of this parasitic bipolar transistor. The channel length dependence of the breakdown voltage of the short channel MOS transistor can then be explained by the dependence of BV CEO on the base width.

J. Moll

Papers

Breakdown mechanism in short-channel MOS transistors