This paper proposes a bin-width tuning method for a field-programmable gate array (FPGA)-based delay line for a time-to-digital converter (TDC). Changing the hit transitions and sampling patterns of the carry chain considering delays of the sum and carry-out bins can improve the bin-width uniformity and thus measurement precision. The proposed sampling method was evaluated and compared with the ordinary tapped-delay-line (TDL) method in three different types of FPGAs: Kintex-7, Virtex-6, and Spartan-6. The linearity, equivalent bin width, and measurement precision improved for all the evaluated FPGAs by adopting the proposed method. The measurement precision obtained using the simple TDL architecture is comparable with other complex TDC architectures. In addition, the proposed method improves bin-width uniformity and measurement precision while maintaining the advantages of TDL TDCs, that is, fast conversion rate and small resource usage. Furthermore, the enhanced linearity of the delay line can also improve other carry-chain-based FPGA-TDCs.

Time-to-Digital Converter Using a Tuned-Delay Line Evaluated in 28-, 40-, and 45-nm FPGAs

Time-to-digital converters (TDCs) are increasingly used as building blocks in biomedical imaging, digital communication, and measurement instrumentation systems. When fabricated in deep-submicrometer (DSM) CMOS technology, TDCs have outstanding time stamping capability on the order of picoseconds. Typically, the timing resolution of a TDC directly determines the minimum resolvable spatial resolution in time-of-flight (ToF) measurements. It also limits the signal-to-noise ratio in ToF positron emission tomography and the in-band noise in an all-digital phase-locked-loop. In TDCs, good linearity and precision result in high measurement accuracy, while the detectable range is limited by its dynamic range. In addition, size and power consumption are of significant importance in large-scale array implementations such as image sensors. Here, we discuss the most recent developments in CMOS TDCs, with an emphasis on ring-oscillator-based TDC and its variants, due to their suitability for array designs with less area overhead. In addition, key performance metrics, and accurate cost-effective characterization methods will be discussed. Finally, future perspectives of CMOS TDCs will be highlighted.

Recent Developments and Design Challenges of High-Performance Ring Oscillator CMOS Time-to-Digital Converters

In this paper, a high resolution, high precision and ultra-low power consumption time-to-digital converter (TDC) is presented. The proposed TDC is based on the gateable Vernier ring oscillator architecture. Fine resolution is achieved through two ring oscillators arranged in the Vernier configuration. This TDC employs a single-transition end-of-conversion detection circuit and turns off the ring oscillators whenever the conversion is completed to reduce power consumption. The prototype chip is fabricated in a standard 130 nm digital CMOS process and its area is only 0.03 ${\rm mm}^{2}$ . Using a 1.2 V supply, the TDC achieves a resolution of 7.3 ps, a single-shot precision of 1.0LSB, and an average power consumption of 1.2 mW. A root-mean-square integral nonlinearity (INL) of 1.2 LSB is obtained with the help of an INL look-up-table calibration. Compared to previously reported ring-oscillator based TDCs, the proposed design achieves the lowest power consumption to date.

A Low-Power Gateable Vernier Ring Oscillator Time-to-Digital Converter for Biomedical Imaging Applications

This paper discusses the construction principles and performance of a pulsed time-of-flight (TOF) laser radar based on high-speed (FWHM $\sim$ 100 ps) and high-energy ( $\sim$ 1 nJ) optical transmitter pulses produced with a specific laser diode working in an “enhanced gain-switching” regime and based on single-photon detection in the receiver. It is shown by analysis and experiments that single-shot precision at the level of 2…3 cm is achievable. The effective measurement rate can exceed 10 kHz to a noncooperative target (20% reflectivity) at a distance of $>\ 50\ \hbox{m}$ , with an effective receiver aperture size of $2.5\ \hbox{cm}^{2} $ . The effect of background illumination is analyzed. It is shown that the gating of the SPAD detector is an effective means to avoid the blocking of the receiver in a high-level background illumination case. A brief comparison with pulsed TOF laser radars employing linear detection techniques is also made.

On Laser Ranging Based on High-Speed/Energy Laser Diode Pulses and Single-Photon Detection Techniques

This paper presents low nonlinearity, compact, and multichannel time-to-digital converters (TDC) in Xilinx 28 nm Virtex 7 and 20 nm UltraScale field-programmable gate arrays (FPGAs). The proposed TDCs integrate several innovative methods that we have developed: 1) the subtapped delay line averaging topology; 2) tap timing tests; 3) a direct compensation architecture; and 4) a mixed calibration method. The code density tests show that the proposed TDCs have much better linearity performances than previously reported ones. Our approach is cost-effective in terms of the consumption of logic resources. To demonstrate this, we implemented 96 channel TDCs in both FPGAs, using less than 25% of the logic resources. The achieved least significant bit (LSB) is 10.5 ps for Virtex 7 and 5.0 ps for UltraScale FPGAs. After the compensation and calibration, the differential nonlinearity (DNL) is within [–0.05, 0.08] LSB with σDNL = 0.01 LSB, and the integral nonlinearity (INL) is within [–0.09, 0.11] LSB with σINL = 0.04 LSB for the Virtex 7 FPGA. The DNL is within [–0.12, 0.11] LSB with σDNL = 0.03 LSB, and the INL is within [–0.15, 0.48] LSB with σINL = 0.20 LSB for the UltraScale FPGA.

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Multichannel, Low Nonlinearity Time-to-Digital Converters Based on 20 and 28 nm FPGAs

A multichannel time-to-digital converter (TDC) implemented with 0.35-μm complementary metal-oxide-semiconductor technology that uses a low-frequency crystal as reference and measures the time intervals with counter and delay line interpolation techniques is described. The multichannel measurement architecture provides information on the time intervals between several timing signals. The circuit can be used for laser time-of-flight distance measurements, e.g., where it can determine time intervals between a transmitted laser pulse and several reflected pulses and also pulsewidths or rise times, to compensate for the timing walk error. This paper shows how several measurement channels can be integrated into one TDC without losing the measurement performance. The circuit offers a measurement precision that is better than 8 ps and a measurement range of up to 74 μs. In terms of laser distance measurement, its performance is equivalent to millimeter-level precision within an 11-km range.

A Multichannel High-Precision CMOS Time-to-Digital Converter for Laser-Scanner-Based Perception Systems

A pulsed time-of-flight laser radar based on a high speed/energy optical transmitter and a SPAD-TDC receiver is presented. The transmitter employs a bulk double heterostructure laser diode operating in enhanced gain switching mode at a wavelength of ∼870nm, giving ∼1nJ/125ps optical pulses. The receiver is a single CMOS chip consisting of a 9×9 CMOS SPAD array and a 10-channel 10ps precision TDC. The 2D detector array releases the required precision and tolerances of the opto-mechanics of the radar. Any of the 3×3 sub-arrays within the 9×9 array can be selected for simultaneous measurement, and the selection can be altered flexibly during measurements, e.g. to follow movements of the target image at the detector surface. Adjustable-width time-gating windows of down to ∼5ns can be used to suppress background hits. A single shot precision of ∼170ps (FWHM) and a measurement range of tens of metres with non-cooperative targets have been achieved with an 18mm receiver aperture.

J-P Jansson

Papers

A Multichannel High-Precision CMOS Time-to-Digital Converter for Laser-Scanner-Based Perception Systems

Pulsed TOF laser rangefinding with a 2D SPAD-TDC receiver