Escalating system-on-chip design complexity is pushing the design community to raise the level of abstraction beyond register transfer level. Despite the unsuccessful adoptions of early generations of commercial high-level synthesis (HLS) systems, we believe that the tipping point for transitioning to HLS msystem-on-chip design complexityethodology is happening now, especially for field-programmable gate array (FPGA) designs. The latest generation of HLS tools has made significant progress in providing wide language coverage and robust compilation technology, platform-based modeling, advancement in core HLS algorithms, and a domain-specific approach. In this paper, we use AutoESL's AutoPilot HLS tool coupled with domain-specific system-level implementation platforms developed by Xilinx as an example to demonstrate the effectiveness of state-of-art C-to-FPGA synthesis solutions targeting multiple application domains. Complex industrial designs targeting Xilinx FPGAs are also presented as case studies, including comparison of HLS solutions versus optimized manual designs. In particular, the experiment on a sphere decoder shows that the HLS solution can achieve an 11-31% reduction in FPGA resource usage with improved design productivity compared to hand-coded design.

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High-Level Synthesis for FPGAs: From Prototyping to Deployment

An integer linear programming (ILP) model for the scheduling problem in high-level synthesis is presented. In addition to time-constrained scheduling and resource-constrained scheduling, a scheduling problem called feasible scheduling, which provides a paradigm for exploring the solution space, is constructed. Extensive consideration is given to the following applications: scheduling with chaining, multicycle operations by nonpipelined function units, and multicycle operations by pipelined function units; functional pipelining; loop folding; mutually exclusive operations; scheduling under bus constraint; and minimizing lifetimes of variables. The complexity of the number of variables in the formulation is O(s*n) where s and n are the number of control steps and operations, respectively. Since the as soon as possible (ASAP), as late as possible (ALAP), and list scheduling techniques are used to reduce the solution space, the formulation becomes very efficient. A solution to a practical problem, such as the fifth-order filter, can be found optimally in a few seconds. >

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A formal approach to the scheduling problem in high level synthesis

ion and Compositional Techniques From Asymmetry to Full Symmetry: New Techniques for Symmetry Reduction in Model Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 E.Allen Emerson, Richard J. Trefler Automatic Error Correction of Large Circuits Using Boolean Decomposition and Abstraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 Dirk W. Hoffmann, Thomas Kropf Abstract BDDs: A Technique for Using Abstraction in Model Checking . . . 172 Edmund Clarke, Somesh Jha, Yuan Lu, Dong WangBDDs: A Technique for Using Abstraction in Model Checking . . . 172 Edmund Clarke, Somesh Jha, Yuan Lu, Dong Wang Theorem Proving Related Approaches Formal Synthesis at the Algorithmic Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 Christian Blumenröhr, Viktor Sabelfeld Xs Are for Trajectory Evaluation, Booleans Are for Theorem Proving . . . . . 202 Mark Aagaard, Thomas Melham, John O’Leary Verification of Infinite State Systems by Compositional Model Checking . . 219 K.L.McMillan Symbolic Simulation/Symbolic Traversal Formal Verification of Designs with Complex Control by Symbolic Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 Gerd Ritter, Hans Eveking, Holger Hinrichsen Hints to Accelerate Symbolic Traversal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 Kavita Ravi, Fabio Somenzi Specification Languages and Methodologies Modeling and Checking Networks of Communicating Real-Time Processes . 265 Jürgen Ruf, Thomas Kropf ”Have I Written Enough Properties?” A Method of Comparison between Specification and Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280 Sagi Katz, Orna Grumberg, Danny Geist Program Slicing of Hardware Description Languages . . . . . . . . . . . . . . . . . . . . 298 E.Clarke, M.Fujita, S.P.Rajan, T.Reps, S.Shankar, T.Teitelbaum Table of

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Correct Hardware Design and Verification Methods

This book presents an excellent collection of contributions addressing different aspects of high-level synthesis from both industry and academia. High-Level Synthesis: from Algorithm to Digital Circuit should be on each designers and CAD developers shelf, as well as on those of project managers who will soon embrace high level design and synthesis for all aspects of digital system design.

High-Level Synthesis: from Algorithm to Digital Circuit

: The satisfiability (SAT) problem is a core problem in mathematical logic and computing theory. In practice, SAT is fundamental in solving many problems in automated reasoning, computer aided design, computer aided manufacturing, machine vision, database, robotics, integrated circuit design, computer architecture design, and computer network design. Traditional methods treat SAT as a discrete, constrained decision problem. In recent years, many optimization methods, parallel algorithms, and practical techniques have been developed for solving SAT. In this survey, we present a general framework (an algorithm space) that integrates existing SAT algorithms into a unified perspective. We describe sequential and parallel SAT algorithms including variable splitting, resolution, local search, global optimization, mathematical programming, and practical SAT algorithms. We give performance evaluation of some existing SAT algorithms. Finally, we provide a set of practical applications of the satisfiability problems.

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Algorithms for the Satisfiability (SAT) Problem: A Survey,

A general scheduling methodology is presented that can be integrated into specialized or general-purpose high-level synthesis systems. An initial version of the force-directed scheduling algorithm at the heart of this methodology was originally presented by the authors in 1987. The latest implementation of the logarithm introduced here reduces the number of functional units, storage units, and buses required by balancing the concurrency of operations assigned to them. The algorithm supports a comprehensive set of constraint types and scheduling modes. These include multicycle and chained operations; mutually exclusive operations; scheduling under fixed global timing constraints with minimization of functional unit costs, minimization of register costs, and minimization of global interconnect requirements; scheduling with local time constraints (on operation pairs); scheduling under fixed hardware resource constraints; functional pipelining; and structural pipeline (use of pipeline functional units). Examples from current literature, one of which was chosen as a benchmark for the 1988 High-Level Synthesis Workshop, are used to illustrate the effectiveness of the approach. >

J.P. Knight

Papers

Force-directed scheduling for the behavioral synthesis of ASICs