An overview is presented of total ionizing dose (TID) effects in MOS and bipolar devices from a historical perspective, focusing primarily on work presented at the annual IEEE Nuclear and Space Radiation Effects Conference (NSREC). From the founding of the IEEE NSREC in 1964 until ~1976, foundational work led to the discovery of TID effects in MOS devices, the characterization of basic charge transport and trapping processes in SiO2, and the development of the first generations of metal-gate radiation-hardened MOS technologies. From ~1977 until ~1985, significant progress was made in the understanding of critical defects and impurities that limit the radiation response of MOS devices. These include O vacancies in SiO2, dangling Si bonds at the Si/SiO2 interface, and hydrogen. In addition, radiation-hardened Si-gate CMOS technologies were developed. From ~1986 until ~1997, a significant focus was placed on understanding postirradiation effects in MOS devices and implementing hardness assurance test methods to qualify devices for use in space systems. Enhanced low-dose-rate sensitivity (ELDRS) was discovered and investigated in linear bipolar devices and integrated circuits. From ~1998 until the present, an increasing focus has been placed on theoretical studies enabled by rapidly advancing computational capabilities, modeling and simulation, effects in ultra-thin oxides and alternative dielectrics to SiO2, and in developing a comprehensive model of ELDRS.

Total Ionizing Dose Effects in MOS and Low-Dose-Rate-Sensitive Linear-Bipolar Devices

Radiation induced flatband voltage shifts are measured at 80°K in MOS capacitors with oxides 6.0-50 nm thick. Previous studies have found that for relatively thick oxides (greater than 20 nm) the flatband voltage changes with radiation dose as the square of the oxide thickness suggesting that the holes created by the ionizing radiation in the oxide are uniformly created and trapped. For the thinner oxides examined in the present work, significantly smaller shifts than predicted by the oxide thickness squared dependence were observed indicating that many of the generated holes are escaping the thin oxide. Physical mechanisms to explain this effect, of which recombination of trapped holes by carrier tunneling appears the most important, are discussed.

Radiation Effects in MOS Capacitors with Very Thin Oxides at 80°K

The radiation response of MOS devices exposed to /sup 60/Co and low-energy ( approximately 10 keV) X-ray irradiation is evaluated as a function of electric field during exposure. Improved charge yield estimates are obtained for /sup 60/Co irradiations at fields below 1 MV/cm by matching voltage shifts due to oxide-trap and interface-trap charge to an E/sup -0.55/ electric field dependence. Combining these improved charge yield estimates and calculated dose enhancement factors, the relative response of X-ray to /sup 60/Co irradiations is accurately predicted for oxide electric fields from 0.03 MV/cm to 5.0 MV/cm. The ability to predict the relative response to X-ray to /sup 60/Co irradiations-should speed acceptance of X-ray testers as a hardness assurance tool. >

Charge yield for cobalt-60 and 10-keV X-ray irradiations of MOS devices

The radiation response of MOS devices has been shown to be dependent on the details of the device processing and of the device design. To produce megaradhard devices process controls have been used and special design considerations have been developed. This paper considers the special problem of hardening IC's for low radiation doses (1-10krad). A worst case calculation of the radiation induced threshold voltage shift shows that it may be possible to guarantee the total dose hardness of MOS IC's for low doses by controlling only the gate oxide and field oxide thickness with no other process controls.

Considerations for Hardening MOS Devices and Circuits for Low Radiation Doses

Radiation-induced charge and interface state generation are measured in MOS capacitors with steam oxide layers typical of standard field oxides and at low fields (<0.1 MV/cm) typical of device applications. Interface state buildup occurs primarily through a "prompt" process and most of the states are "slow". Free electron-hole pair yield at low fields is reduced from that previously measured in thinner (gate) oxides.

Charge and Interface State Generation in Field Oxides

Charge buildup in irradiated MOS devices is significantly more severe at low temperatures than at room temperature. Approaches for counteracting this problem are considered in this paper, including: (1) careful selection of the applied field; (2) ion implantation of the oxide; (3) use of a thin oxide. Experimental and analytical results are presented and it is demonstrated that the applied field dependence of flatband voltage shift in MOS capacitors irradiated at 77°K can be accounted for in terms of the field dependence of electron yield and the transport of holes at high fields. Analysis of ion implantation effects indicates that a significant improvement in radiation tolerance should be achievable by this method. A simultaneous consideration of the effects of oxide thickness and applied field on charge buildup in an unimplanted oxide suggests that reducing the thickness to ?500 A° will largely eliminate low temperature problems in a steady-state ionizing radiation environment as long as the applied voltage is ? 10V.

J. R. Srour

Papers

MOS Hardening Approaches for Low-Temperature Applications