Functional test is long viewed as unfitted for production test. The purpose of this contribution is to propose a RTL-based test generation methodology which can be rewardingly used both for design validation and to enhance the test effectiveness of classic, gate-level test generation. Hence, a RTL-based defect-oriented test generation methodology is proposed, for which a high defects coverage (DC) and a relatively short test sequence can be derived, thus allowing low-energy operation in test mode. The test effectiveness, regarding DC, is shown to be weakly dependent on the structural implementation of the behavioral description. The usefulness of the methodology is ascertained using the VeriDOS simulation environment and the CMUDSP ITC'99 benchmark circuit.

http://www.ieee-ets.org/past_events/etw00/Program/Session9A/etw9A_1.pdf

RTL-based functional test generation for high defects coverage in digital SOCs

The purpose of this paper is to present a novel methodology for assessing the quality of architecture solutions of hw/sw systems, with particular emphasis on testability. Criteria and metrics for quality assessment are proposed and used to assist the design team in selecting a ‘best-fitted’ architecture that satisfies not only functional requirements, but also test requirements. The methodology makes use of object-oriented modeling techniques. Near-optimum clustering of methods and attributes into objects is carried out, in such a way that objects with moderate complexity, low coupling and high functional autonomy, result. The main features of the methodology are ascertained through a case study.

Metrics and Criteria for Quality Assessment of Testable Hw/Sw Systems Architectures

Functional test has long been viewed as unfitted for high-quality production test. The purpose of this paper is to propose a RTL-based test generation methodology which can rewardingly be used both for design validation and to enhance the test effectiveness of classic, gate-level test generation. The proposed methodology leads to high Defects Coverage (DC) and to relatively short test sequences, thus allowing low-energy operation in test mode. The test effectiveness, regarding DC, is shown to be weakly dependent on the structural implementation of the behavioral description. The usefulness of the methodology is ascertained using the VeriDOS simulation environment and the CMUDSP and Torch ITC'99 benchmark circuits.

RTL-Based Functional Test Generation for High Defects Coverage in Digital Systems

At present, the functional verification of a device represents the highest cost during manufacturing. To reduce that cost, several methods have been suggested. In this work we propose a method which produces a set of binary test sequences by means of a Compact binary Differential Evolution algorithm (Compact-BinDE). The strategy employed is based on the use of coverage models and cost functions in the verification process, which are built with relevant conditions or coverage points representing the full device behavior. The main problem is to cover all difficult situations since the relationships between the test points and the input data in the design are not trivial. The test generation method is included with a proposed verification platform based on a simulation representing a hybrid method. The main contribution of this work is that the method obtains test vector sequences that maximize the coverage percentage on run-time device simulation with an efficient search in the binary domain. Also, different to the previous works that used meta-heuristics, the proposed method by means of the Compact-BinDE algorithm can reduce the simulation time used to obtain test sequences that exercise the coverage points. The results show that the proposed method represents a good alternative to generate test sequences to cover the coverage points during the functional verification.

Automated Functional Test Generation for Digital Systems Through a Compact Binary Differential Evolution Algorithm

The purpose of this paper is to present a RTL design and test methodology allowing the identification of design errors and difficult to verify functional parts.Using novel RTL fault models (namely, for arithmetic and relational operators) and Testability Metrics, two approaches are combined: RTL DFT and TPG. RTL Design for Testability is illustrated through TPI (Test Point Insertion). RTL Test Pattern Generation is performed using the property that strong correlation exists between n-detection of RT-level faults and single detection of physical defects. The derived functional test leads to high Defects Coverage, DC, when the RTL description is synthesized into a physical layout. The proposed methodology enables tradeoff analysis, for different DFT solutions, or test pattern sequences. The resulting test patterns are, in fact, loosely deterministic patterns, suitable for low-cost BIST implementation. The usefulness of the methodology is ascertained using the mixed-level VeriDOS fault simulation tool and modules from the CMUDSP and TORCH ITC '99 benchmark circuits.

RTL design validation, DFT and test pattern generation for high defects coverage

Describes test quality measures that quantify the completeness of a functional test. The measures are based on exercising a functional model of the unit with the given set of test sequences. Two metrics are proposed: the control-flow coverage (FC1) indicates how completely the logical flow of the functional model is traversed, and the data path coverage (FC2) indicates how completely the data paths have been exercised over a specified set of observable values. The metrics were evaluated using an RTL model of a RISC processor and a combinational circuit. >

J.R. Wallack

Papers

Coverage metrics for functional tests