Efficient access to on-chip instrumentation is a key requirement for post-silicon validation, test, debug, bringup, and diagnosis. Reconfigurable scan networks, as proposed by, for example, IEEE Std 1687-2014 and IEEE Std 1149.1-2013, emerge as an effective and affordable means to cope with the increasing complexity of on-chip infrastructure.Reconfigurable scan networks are often hierarchical and may have complex structural and functional dependencies. Common approaches for scan verification based on static structural analysis and functional simulation are not sufficient to ensure correct operation of these types of architectures. To access an instrument in a reconfigurable scan network, a scan-in bit sequence must be generated according to the current state and structure of the network. Due to sequential and combinational dependencies, the access pattern generation process (pattern retargeting) poses a complex decision and optimization problem.This article presents the first generalized formal model that considers structural and functional dependencies of reconfigurable scan networks and is directly applicable to 1687-2014-based and 1149.1-2013-based scan architectures. This model enables efficient formal verification of complex scan networks, as well as automatic generation of access patterns. The proposed pattern generation method supports concurrent access to multiple target scan registers (access merging) and generates short scan-in sequences.

Reconfigurable Scan Networks: Modeling, Verification, and Optimal Pattern Generation

Reconfigurable scan architectures allow flexible integration and efficient access to infrastructure in SoCs, e.g. for test, diagnosis, repair or debug. Such scan networks are often hierarchical and have complex structural and functional dependencies. For instance, the IEEE P1687 proposal, known as IJTAG, allows integration of multiplexed scan networks with arbitrary internal control signals. Common approaches for scan verification based on static structural analysis and functional simulation are not sufficient to ensure correct operation of these types of architectures. Hierarchy and flexibility may result in complex or even contradicting configuration requirements to access single elements. Sequential logic justification is therefore mandatory both to verify the validity of a scan network, and to generate the required access sequences. This work presents a formal method for verification of reconfigurable scan architectures, as well as pattern retargeting, i.e. generation of required scan-in data. The method is based on a formal model of structural and functional dependencies. Network verification and pattern retargeting is mapped to a Boolean satisfiability problem, which enables the use of efficient SAT solvers to exhaustively explore the search space of valid scan configurations.

Modeling, verification and pattern generation for reconfigurable scan networks

The application of SOC-style test partitioning to a monolithic microprocessor design results in considerable benefits, including simpler and faster ATPG, reduced ECO impact, faster debug, and, most surprisingly, reduced test application time. These results challenge the orthodoxy that flat, top-level ATPG is the best method to produce an optimal pattern set. The granularity of the partitioning was the key factor in achieving the results: a 33-element partition of the AMDtrade Athlon CPU chip resulted in better than a ~80% reduction in test time compared to aflat model of the entire chip. This paper describes the ATPG experiments and quantifies the design overhead required for implementing wrapper cells at partition boundaries.

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Test cost reduction for the AMD™ Athlon processor using test partitioning

We describe a novel method to partition flip-flops in scan chains into disjoint groups of flip-flops that are to be driven by independent scan enable signals to achieve higher delay fault coverage. The proposed method to partition flip-flops is motivated by our recent work which demonstrated that driving subsets of flip-flops by independent scan enable signals to launch signal transitions will lead to higher delay fault coverage by broadside tests. As in broadside test none of the scan enable signals need to switch at-speed. Experimental results for delay fault coverage improvement on larger ISCAS-89 benchmark and industrial circuits are presented

Improved Delay Fault Coverage Using Subsets of Flip-flops to Launch Transitions

Cost effective SOC test strongly hinges on parallel, independent test of SOC cores, which can only be ensured through proper core isolation techniques. While a core isolation mechanism can provide controllability and observability at the core I/O interface, its implementation may have various implications on area, functional timing, test time and data volume, and at-speed coverage on the core interface. This paper proposed a non-intrusive core isolation technique that is based on the utilization of existing core registers for isolating the core. The authors provide a core register partitioning algorithm that is capable of identifying the core interface registers, and of robustly isolating a core, resulting in a computationally efficient core isolation implementation that is area and performance efficient at the same time. The proposed isolation technique also ensures minimal test time increase and no at-speed coverage loss on the core interface, offering an elegant solution for soft cores, and thus enabling significant SOC test cost reductions

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A non-intrusive isolation approach for soft cores

A hierarchical approach to DFT is presented to address the issues encountered when inserting DFT into large SOC designs. There were challenges in implementing this methodology and the real motivation for implementation of a hierarchical DFT is to align with front-end and physical design process. Implementation of this method includes reduced runtime of tools and reduced pattern size. As a result of additional tester memory available using this technique, more testing was implemented. The case study uses a production design with sandburst, Inc (0.13 /spl mu/, 4 Mgate chip).

J. Remmers

Papers

Hierarchical DFT methodology - a case study