A tutorial review of a classic paper by Samuel J. Mason (1954) is described. That paper contained the first definition of a unilateral power gain for a linear two-port and the first proof that this grain is invariant with respect to linear lossless reciprocal four-port embeddings, thereby making it useful as a figure of merit intrinsic to the device. In this work, that original paper is brought up to date, a tutorial exposition of its contents is presented in a modern form, and its significance and applications in microwave engineering are discussed. The subsequent advances in the subject area are summarized, so that the original paper can be placed within a broader context and understood with a more general perspective. >

Power gain in feedback amplifiers, a classic revisited

The downscaling of CMOS processes has led to devices with an impressive RF performance. Advanced nanoscale RF MOSFETs present very high transit frequency, which can be traded off with lower power consumption, by shifting the operating point towards the weak inversion (WI) regime. This paper explores whether the simple RF schematics and models used in strong inversion remain valid in moderate or even down to deep WI regions for nanoscale devices. A simple RF equivalent circuit is proposed, leading to first-order analytical expressions, which are able to describe the RF small-signal behavior of nanoscale MOSFET, including noise, across all inversion levels. Using these expressions it is possible to extract the values of all the RF components and noise model parameters directly from measurements. The analytical models are compared to RF measurements of a commercial state-of-the-art 40-nm CMOS process and to the advanced BSIM6 compact bulk MOSFET model, showing very good accuracy.

RF Small-Signal and Noise Modeling Including Parameter Extraction of Nanoscale MOSFET From Weak to Strong Inversion

The evolution and characteristics of the electronics is directly linked to the technological and societal progress. Today, there is a huge variety of electronic solutions offered, with the RF low-power systems, such as wireless sensor networks, wireless body area networks and the Internet of Things (IoT), to gain more and more ground. However, these RF low-power applications set stringent constraints on the power consumption, which complicate even more the already difficult task of the RF IC design. This can be addressed by exploiting the phenomenal RF performance offered by the state-of-the-art nanoscale CMOS technologies, with impressive peak transit frequency at the order of hundreds of GHz, and sub-1 dB minimum noise figure. More specifically, most of the RF applications operate at the low GHz range, so the cut-off frequency surplus, achieved typically in strong-inversion (SI), can be traded-off with a lower power consumption by shifting the operating point to moderate- (MI) or weak-inversion (WI), while keeping the RF performance within the desired specifications. There is an extensive work by the semiconductor community on characterization and modeling the MOS transistor at RF. Nonetheless, most of such studies focus either on the high-performance SI or on rather mature processes with respect to the contemporary state-of-the-art. In this thesis, an extensive and multi-faceted work on detailed characterization and accurate modeling of nanoscale MOSFETs for low-power operation, focusing therefore on subthreshold operation, is presented and discussed. The analysis is always performed under the perspective of the ultra-low power RF IC design. After all, the reliability of the RF IC simulation tools in this high-end range of frequencies and at very low current densities, which constitute the two extreme conditions in terms of operation of the transistor, strongly depends on the accuracy of the model used. The dissertation follows a dual course. First, a simple, yet thorough, small-signal RF model is elaborated in order, to describe analytically the RF performance of nanoscale MOSFETs from SI down to the deep WI region, including its noise behavior. Further, the analytical expressions are used in order to form a step-by-step parameter extraction methodology. Especially, for the extraction of the RF noise model parameters, an innovative step-by-step procedure, which is applied directly on measurements, is developed. Then, a state-of-the-art physics-based compact model (BSIM6) is used. Within this part of the work, a set of novel advancements and contributions are introduced in order for the model to be able to capture the complexity of the behavior of modern advanced CMOS technologies. The results show excellent agreement regarding all different aspects, across all modes of operation (CV, DC, RF performance), even at very low bias conditions. The evaluation of both the modeling approaches is done in detail and uses design oriented tools and metrics, such as the Gm/ID, the Y-parameters, the four RF noise parameters and a wide range of figures-of-merit (FoMs). Finally, a discussion around inversion coefficient (IC) design methodology is carried out, where several FoMs based on IC are modeled with the use of very simple analytical expressions requiring only few parameters. Measurements of advanced 40 nm and 28 nm CMOS technologies are used throughout the thesis to validate all the different modeling approaches.

Characterization and modeling of nanoscale MOSFET for ultra-low power RF IC design

The state-of-the-art scaled down CMOS processes have led to devices with extremely high Ft reaching several hundreds of GHz. This high Ft can be traded with power consumption by moving the operating point towards weak inversion with Ft reaching tens of GHz, high enough for many modern RF applications. The new charge-based bulk compact MOSFET model BSIM6 was developed with the objective to provide an accurate description of the modern nanoscale CMOS technologies including weak and moderate inversion regions. This paper, compares BSIM6 against RF measurements made on an advanced 40 nm CMOS process, particularly focusing on very low bias conditions. The results validate the model's accuracy and demonstrate its suitability for ultra-low power RF IC design.

Low-power RF modeling of a 40nm CMOS technology using BSIM6

Logic CMOS-based RF technology is introduced for a 10-Gb transceiver in which active and passive RF devices have been realized in a single chip. RF nMOS of 115-GHz fT, 100-GHz fmax, and sub-1.0-dB NFmin at 10 GHz have been fabricated by aggressive device scaling and layout optimization. High-Q MiM capacitor and spiral Cu inductors have been successfully implemented in the same chip by 0.13-mum low-K/Cu back end of integration line technology. Core 1.0 V MOS and/or junction varactors for VCO at 10 GHz are offerings free of extra cost and realized by the elaborated layout

https://ir.nctu.edu.tw:443/bitstream/11536/11994/1/000239706300006.pdf

Low-K/Cu CMOS-based SoC technology with 115-GHz f/sub T/, 100-GHz f/sub max/, low noise 80-nm RF CMOS, high-Q MiM capacitor, and spiral Cu inductor

The unilateral gain defined by S. J. Mason, is a basic measure of the transfer activity of a two-port. It can be measured in a circuit made unilateral with lossless reciprocal elements. A general method of measurement is described, which in principle uses two reactances only; no transformers are required. The method has been realized in a coaxial-line circuit, and measurements have been made on a few transistors in the frequency range 100 to 900 Mc . The results confirm that the unilateral gain is indeed measured in this circuit. It is suggested that unilateral gain measurements are useful both for research into basic device performance and for the specification of power-amplifying ability.

J. Rollett

Papers

The Measurement of Transistor Unilateral Gain